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Teilenummer | OXU140CM |
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Beschreibung | USB On-The-Go Full Speed Host | |
Hersteller | Oxford Semiconductor | |
Logo | ||
Gesamt 20 Seiten www.DataSheet4U.com
Data Sheet
OXU140CM
USB On-The-Go Full Speed Host, High Speed Peripheral
with Multi-Storage Interface
Features
Single‐chip USB OTG full‐speed host and high‐speed peripheral
controller
Reduces system cost and board space
Minimizes system design complexity and power
Simultaneous USB host, peripheral, and
CE‐ATA/MMC/SD interface operation
USB peripheral to CE‐ATA/MMC/SD bridging
Compatible with the USB 2.0 and OTG specifications
CE‐ATA 1.1 command support with built‐in flow control
MMC 4.1 compatible
Configurable 1‐/4‐/8‐bit data bus at up to 48 MHz clock
frequency
Dual‐voltage (3.3 V and 1.8 V) I/O support
Integrated smart clock control for reduced power
consumption
3.3 V power supply, flexible I/O voltage of 1.65 V to 3.6 V
(LVCMOS/TTL) to interface to a wide range of MCUs
Low‐power sleep mode to minimize power consumption when
not in use
Integrated on‐chip charge pump, supports up to 100 mA of
current, enables support for broad range of USB devices
Packaging
8 × 8 mm BGA, 100 ball, RoHS compliant
14 × 14 mm LQFP, 128 pin, RoHS compliant
16‐bit memory mapped interface can gluelessly interface to most
popular microprocessors and DSPs
Fast microprocessor access cycle and double/multi buffering
support for all four types of USB transfers
Two DMA (slave) channel support for peripheral controller and
CE‐ATA/MMC/SD controller lowers CPU utilization
Integrated PLL supports external crystal or crystal oscillators of
12 MHz or 30 MHz, for system flexibility
DS-0038 Jul 06
External--Free Release
1
OXU140CM Data Sheet
Oxford Semiconductor, Inc.
Table 4 DC Characteristics, High-Speed USB I/O Signals: DPP and DMP Only
Symbol
Parameter
Condition
VHSDIFF High-speed differential input
sensitivity
|VI(DPP) -- VI(DMP)|
VHSCM
High-speed data signaling
common mode range
VHSSQ
High-speed squelch detection
threshold
Squelch detected
No squelch detected
VHSIO
High-speed idle output voltage
(differential)
VHSOL
High-speed low-level output
voltage (differential)
VHSOH
High-speed high-level output
voltage (differential)
VCHIRPK Chirp-K output voltage
(differential)
Min Max Unit
300 mV
-50 500 mV
100 mV
150 mV
-10 10 mV
-10 10 mV
-360 400 mV
-900 -500 mV
Table 5 DC Characteristics, Logic Signals
Symbol
VOL
VOH
Parameter
Low-level output voltage
High-level output voltage
VIL Low-level input voltage
VIH High-level input voltage
CIN
COUT
CBI
IIN
Input capacitance
Output capacitance
Bi-directional capacitance
Input leakage current
Condition
VDDW = 3.3 V
VDDW = 1.8 V
VDDW = 3.3 V
VDDW = 1.8 V
VDDW = 3.3 V
VDDW = 1.8 V
No pull up or pull down
Min Max
0.4
2.4
0.75*VDDW
0.8
0.3*VDDW
2.0
0.7*VDDW
2.2 (typical)
2.2 (typical)
2.2 (typical)
-10 10
Unit
V
V
V
V
V
V
V
pF
pF
pF
µA
Note:
The capacitances listed above do not include pad capacitance and package capacitance.
One can estimate pin capacitance by adding pad capacitance of about 0.5 pF; and the
package capacitance, which is about 0.86 pF max for QFP and 0.42 pF max for BGA.
Table 6 DC Characteristics, ID Resistance
Symbol
RB-PLUG-ID
RA-PLUG-ID
Parameter
Resistance to ground on mini-B plug
Resistance to ground on mini-A plug
Condition
Min Max Unit
100 K
Ω
10 Ω
6
External--Free Release
DS-0038 Jul 06
6 Page OXU140CM Data Sheet
Oxford Semiconductor, Inc.
Table 13 OXU140CM 128-Pin LQFP Pin Allocations (Sheet 3 of 3)
Pin No. Type(1)
Pins
Name
Description
Internal Voltage Regulator (2 pins)
104
1I
ENVREG
105
1O
VREGOUT
Enables the internal voltage regulator if asserted. If
not used, this pin should be tied to VSS
Internal voltage regulator output of 1.8 V. If enabled,
this output should be connected to the VDD1.8
supplies of the chip. If the regulator is disabled, this
pin should be treated as another VDD1.8 supply input
to the chip
Test (2 pins)
83
1I
XMODE
Xcrv test mode. This pin should be grounded for
normal operation
113
1 ID
TEST
Factory test mode. This pin should be grounded or
left floating (has an internal pull-down) for normal
operation
Miscellaneous (11 pins)
55, 57, 59, 69, 70, 1
71 72, 96, 99,
100,111
NC
No connection. These pins should be left floating
Note to Table 13:
1 Type key: format is [(L)(W_)X(Y)(_Z(T))] where the following conventions apply:
L—Logic Level
M(2) Multi-voltage:
3.3 V CMOS
2.5 V CMOS
1.8 V CMOS
S Schmitt Trigger
W—Tolerance
5 5V
3.3 V
X—Type
I Input
O Output
B Bidirectional
Y—Pull
U Pull up
D Pull down
Z—Drive
C(3)
None
T—Tristate
T Tristate
Normal
2 Program to 3.3 V, 2.5 V, or 1.8 V by setting the VIO voltage level.
3 Program to 2 mA, 4 mA, 6 mA, 8 mA, 10 mA, 12 mA, 14 mA, or 16 mA.
12
External--Free Release
DS-0038 Jul 06
12 Page | ||
Seiten | Gesamt 20 Seiten | |
PDF Download | [ OXU140CM Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
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