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PDF OX9162 Data sheet ( Hoja de datos )
| Número de pieza | OX9162 | |
| Descripción | Integrated Parallel Port/Local Bus and PCI interface | |
| Fabricantes | Oxford Semiconductor | |
| Logotipo |  |
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FEATURE
• 8 bit pass-through local bus
• IEEE1284 SPP/EPP/ECP parallel port
• Single function target PCI controller, fully PCI 2.2 and
PCI Power Management 1.0 compliant
DESCRIPTION
The OX9162 is a single chip solution for PCI-based parallel
expansion add-in cards, or local bus bridges. It is a single
function PCI device, where function 0 offers either an 8 bit
Local Bus or a bi-directional parallel port.
For legacy applications the PCI resources are arranged so
that the parallel port can be located at standard I/O
addresses.
The efficient 32-bit, 33MHz target-only PCI interface is
compliant with version 2.2 of the PCI Bus Specification and
version 1.0 of PCI Power Management Specification. For
OX9162
Integrated Parallel Port/Local
Bus and PCI interface
• 2 multi-purpose IO pins which can be configured as
interrupt input pins
• Can be reconfigured using optional non-volatile
configuration memory (EEPROM)
• 5.0V operation
• 128 TQFP package
full flexibility, all the default register values can be
overwritten using an optional MicrowireTM serial EEPROM.
Bridging applications can be realised using the 8-bit pass-
through Local Bus function. The addressable space can be
increased up to 256 bytes for each chip-select region.
The OX9162 alternatively provides an IEEE1284 EPP/ECP
parallel port which fully supports the existing Centronics
interface. The parallel port can be enabled in place of the
Local Bus.
Oxford Semiconductor Ltd.
69 Milton Park, Abingdon, Oxon, OX14 4RX, UK
Tel: +44 (0)1235 824900 Fax: +44(0)1235 821141
© Oxford Semiconductor 1999
OX9162 1.0 PRELIMINARY – October 1999
Part No. OX9162-TQC-A
1 page  
OXFORD SEMICONDUCTOR LTD.
OX9162
Mode
Dir1 Name
Parallel
Local Bus
Local Bus
N/A 62 O LBRST
61 O LBRST#
83 O LBDOUT
101
99, 91
63
85
77,78,79,82,
87,88,89,90
66,67,68,71,
72,73,74,76
O LBCLK
O LBCS[1:0]#
O LBDS[1:0]#
O LBWR#
O LBRDWR#
O LBRD#
O Hi
O LBA[7:0]
I/O LBD[7:0]
Description
Local bus active-high reset
Local bus active-low reset
Local bus data out enable. This pin can be used by external
transceivers; it is high when LBD[7:0] are in output mode and
low when they are in input mode.
Buffered PCI clock. Can be enabled / disabled by software
Local bus active-low Chip-Select (Intel mode)
Local bus active-low Data-Strobe (Motorola mode)
Local Bus active-low write-strobe (Intel mode)
Local Bus Read-not-Write control (Motorola mode)
Local Bus active-low read-strobe (Intel mode)
Permanent high (Motorola mode)
Local bus address signals
Local bus data signals
Data Sheet Revision 1.1 PRELIMINARY
Page 5
5 Page 
OXFORD SEMICONDUCTOR LTD.
OX9162
4.3 Accessing logical functions
Access to the local bus and parallel port is achieved via standard I/O and memory mapping, at addresses defined by the Base
Address Registers (BARs) in configuration space. The BARs are configured by the system to allocate blocks of I/O and memory
space to the logical function, according to the size required by the function. The addresses allocated can then be used to access
the function. The mapping of these BARs is shown in Table 4.
BAR Function 0
Local Bus
Parallel Port
0
CS0 (I/O mapped)
Parallel port base registers (I/O mapped)
1
CS1 (I/O mapped)
Parallel port extended registers (I/O mapped)
2 Local configuration registers (I/O mapped
3 Local configuration registers (memory mapped)
4 All CS (memory mapped
Unused
5 Unused
Table 4: Base Address Register definition
4.3.1 PCI access to 8-bit local bus
When the local bus is enabled (Mode 1), the function
reserves two blocks of I/O space (BAR0 for chip select 0,
BAR1 for chip select 1) and a block of memory space
(BAR4 for chip selects 0 and 1). Each I/O block size is user
definable in the range of 4 to 256 bytes; the memory range
is fixed at 4K bytes.
I/O space
In order to minimise the usage of IO space, the block sizes
for BAR0 and BAR1 are user definable in the range of 4 to
256 bytes.
The 8-bit Local Bus has eight address lines (LBA[7:0])
which correspond to the maximum IO address space. If the
maximum allowable block size is allocated to the IO space
(i.e. 256 bytes), then as access in IO space is byte aligned,
LBA[7:0] equal PCI AD[7:0] respectively. When the user
selects an address range which is less than 256 bytes, the
corresponding upper address lines will be set to logic zero.
Memory Space:
The memory base address registers have an allocated
fixed size of 4K bytes in the address space. Since the
Local Bus has 8 address lines and the OX9162 only
implements DWORD aligned accesses in memory space,
the 256 bytes of addressable space per chip select is
expanded to 1K. Unlike an I/O access (where access to
BAR0, BAR1 determines chip-select decoding) for a
memory access the internal chip-select decoding logic
uses the field PCI AD[10] to decode into 2 chip-select
regions. When the Local Bus is accessed in memory
space, A[9:2] are asserted on LBA[7:0]. The chip-select
regions are defined below.
Local Bus
Chip-Select
LBCS0# (LBDS0#)
LBCS1# (LBDS1#)
PCI Offset from BAR 1 in
Function1 (Memory space)
Lower Address Upper Limit
000h 3FCh
400h 7FCh
Table 5: PCI address map for local bus (memory)
Note: The description given for I/O and memory accesses
is for an Intel-type configuration for the Local Bus. For
Motorola-type configuration, the chip select pins are
redefined to data strobe pins. In this mode the Local Bus
offers up to 8 address lines and two data-strobe pins.
4.3.2 PCI access to parallel port
When the parallel port is enabled (Mode 0), access to the
port works via BAR definitions as usual with two I/O BARs
corresponding to the two sets of registers defined to
operate an IEEE1284 ECP/EPP and bi-directional Parallel
Port.
The user can change the I/O space block size of BAR0 or
BAR1 as for the local bus mode by over-writing the default
values using the serial EEPROM (see section 4.4).
Legacy parallel ports expect the upper register set to be
mapped 0x400 above the base block, therefore if the BARs
are fixed with this relationship, generic parallel port drivers
can be used to operate the device in all modes.
Example: BAR0 = 0x00000379 (8 bytes at address 0x378)
BAR1 = 0x00000779 (8 bytes at address 0x778)
If this relationship is not used, custom drivers will be
needed.
Data Sheet Revision 1.1 PRELIMINARY
Page 11
11 Page | ||
| Páginas | Total 41 Páginas | |
| PDF Descargar | [ Datasheet OX9162.PDF ] | |
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