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OX16PCI954 Schematic ( PDF Datasheet ) - Oxford Semiconductor

Teilenummer OX16PCI954
Beschreibung Integrated Quad UART and PCI interface
Hersteller Oxford Semiconductor
Logo Oxford Semiconductor Logo 




Gesamt 30 Seiten
OX16PCI954 Datasheet, Funktion
www.DataSheet4U.com
FEATURES
Four 16C950 High performance UART channels
8/32-bit Pass-through Local Bus
IEEE1284 EPP parallel port
Multi-function target PCI controller, fully PCI 2.2 and
PCI Power Management 1.0 compliant
UARTs fully software compatible with 16C550-type
devices.
Baud rates up to 15Mbps in asynchronous mode and
60Mbps in external 1x clock mode
128-byte deep FIFO per transmitter and receiver
Flexible clock prescaler from 1 to 31.875
Automated in-band flow control using programmable
Xon/Xoff in both directions
Automated out-of-band flow control using CTS#/RTS#
and/or DSR#/DTR#
DESCRIPTION
The OX16PCI954 is a single chip solution for PCI-based
serial and parallel expansion add-in cards. It is a dual
function PCI device, where function 0 offers four ultra-high
performance OX16C950 UARTs, and function 1 is
configurable to offer either an 8 bit Local Bus or a bi-
directional parallel port. Serial port cards with up to 8 ports
(or with 4 serial ports and a parallel port) can be designed
without redefining any device or timing parameters.
Each channel in the OX16PCI954, the fastest available
PC-compatible UART, offers data rates up to 15Mbps and
128-deep transmitter and receiver FIFOs. Deep FIFOs
reduce CPU overhead and allow utilisation of higher data
rates. Each channel is software compatible with the widely
used industry-standard 16C550 devices and compatibles
as well as the OX16C95x family of high performance
UARTs. In addition to increased performance and FIFO
size, the UARTs also provide the full set of OX16C95x
enhanced features including automated in-band flow
control, readable FIFO levels etc.
The efficient 32-bit, 33MHz target-only PCI interface is
compliant with version 2.2 of the PCI Bus Specification and
version 1.0 of PCI Power Management Specification. For
applications that do not require the internal parallel port or
the local Bus, card designers can assign a Subsystem
Vendor ID and a Subsystem ID using 32 input pins. If the
UARTs are not required, the Local Bus can be extended
from 8-bit operation to a full 32-bit pass-through interface.
OX16PCI954
Integrated Quad UART
and PCI interface
Arbitrary trigger levels for receiver and transmitter
FIFO interrupts and automatic in-band and out-of-
band flow control
Infra-red (IrDA) receiver and transmitter operation
9-bit data framing as well as 5,6,7 and 8
12 multi-purpose IO pins which can be configured as
interrupt input pins
Can be reconfigured using optional non-volatile
configuration memory (EEPROM)
Global Interrupt Status and readable FIFO levels to
facilitate implementation of efficient device drivers
Operation via IO or memory mapping.
Detection of bad data in the receiver FIFO
5.0V operation
160 TQFP package
For full flexibility, all the default register values can be
overwritten using an optional MicrowireTM serial EEPROM.
To enhance device driver efficiency and reduce interrupt
latency, internal UARTs have multi-port features such as
shadowed FIFO fill levels, a global interrupt source register
and Good-Data Status, readable in four adjacent DWORD
registers visible to logical functions in IO space and
memory space.
Expansion of serial cards beyond four channels is possible
using the 8-bit pass-through Local Bus function. The
addressable space can be increased up to 256 bytes, and
divided into four chip-select regions. In 32-bit mode the bus
can map up to 16kb of Memory address space. This
flexible expansion scheme caters for cards with up to 20
serial ports using external 16C950, 16C952, 16C954 or
compatible devices, for composite applications such as
combined serial and parallel port expansion cards.
The OX16PCI954 also provides an IEEE1284 EPP parallel
port which fully supports the existing Centronics interface.
The parallel port can be enabled in place of the Local Bus.
Oxford Semiconductor Ltd.
69 Milton Park, Abingdon, Oxon, OX14 4RX, UK
Tel: +44 (0)1235 824900 Fax: +44(0)1235 821141
© Oxford Semiconductor 1999
OX16PCI954 Data Sheet Revision 1.3 – Feb. 1999
Part No. OX16PCI954-TQC60-A






OX16PCI954 Datasheet, Funktion
OXFORD SEMICONDUCTOR LTD.
OX16PCI954
Power management:
OX16PCI954 complies with PCI Power Management
Specification 1.0 and PC98/99 Power Management
specifications. Both functions offer the extended
capabilities for Power Management. This achieves
significant power saving by enabling device drivers to
power down the PCI function and the channel clock (in
power state D3). Wake-up is requested via PME# from RI
in power-state D3 or any modem line and SIN in power-
state D2.
Optional EEPROM:
OX16PCI954 can be reconfigured from an external
EEPROM. However, this is not required in many
applications as default values are provided for typical
applications up to 8 serial ports, and in some cases the
2 BLOCK DIAGRAM
Subsystem ID and Subsystem Vendor ID can be set via
input pins.
Multi-function device:
OX16PCI954 is a multi-function device to enable users to
load individual device drivers for internal serial ports, the
internal parallel port and peripheral devices connected to
the Local Bus.
Quad Internal OX16C950 UARTs
OX16PCI954 contains four ultra-high performance UARTs,
which can increase driver efficiency using features such as
128-byte deep transmitter & receiver FIFOs, data rates up
to 60Mbps, flexible clock options, automatic flow control,
programmable interrupt and flow control trigger levels and
readable FIFO levels.
MODE[1:0]
FIFOSEL
AD[31:0]
C/BE[3:0]#
CLK
FRAME#
DEVSEL#
IRDY#
TRDY#
STOP#
PAR
SERR#
PERR#
IDSEL
RST#
INTA#
INTB#
PME#
XTALO
XTALI
UART_Ck_Out
LBCLK
EE_DO
EE_DI
EE_CK
EE_CS
Config.
interface
Function
0
Quad
UARTs
PCI
interface
Interrupt
logic
MIO pins
Parallel
port
Clock &
Baud rate
generator
EEPROM
interface
Function
1
Local
Bus
Figure 1: OX16PCI954 Block Diagram
SOUT[3:0]
SIN[3:0]
RTS[3:0]#
DTR[3:0]#
CTS[3:0]#
DSR[3:0]#
DCD[3:0]#
RI[3:0]#
MIO[11:0]
PD[7:0]
ACK#
PE
BUSY
SLCT
ERR#
SLIN#
INIT#
AFD#
STB#
LBA[7:0]
LBD[7:0]
LBCS[3:0]
LBWR#
LBRD#
LBRST
Data Sheet Revision 1.3
Page 6

6 Page









OX16PCI954 pdf, datenblatt
OXFORD SEMICONDUCTOR LTD.
OX16PCI954
Note 1: Direction key:
I Input
IU Input with internal pull-up
O Output
I/O Bi-directional
OD Open drain
NC No connect
Z High impedance
P_I
P_O
P_I/O
P_OD
PCI input
PCI output
PCI bi-directional
PCI open drain
G Ground
V 5.0V power
Note 2: Power & Ground
There are two GND and two VDD rails internally. One set of rails supply power and ground to output buffers while in switching
state (called AC power) and another rail supply the core logic, input buffers and output buffers in steady-state (called DC rail).
The rails are not connected internally. This precaution reduces the effects of simultaneous switching outputs and undesirable RF
radiation from the chip. Further precaution is taken by segmenting the GND and VDD AC rails to isolate the PCI, Local Bus and
UART pins.
Data Sheet Revision 1.3
Page 12

12 Page





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