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YMF743 Schematic ( PDF Datasheet ) - YAMAHA CORPORATION

Teilenummer YMF743
Beschreibung Audio CODEC
Hersteller YAMAHA CORPORATION
Logo YAMAHA CORPORATION Logo 




Gesamt 24 Seiten
YMF743 Datasheet, Funktion
www.DataSheet4U.com
YMF743
AC’97 Revsion2.1 Audio CODEC
with Digital Audio I/F
OVERVIEW
YMF743 is an AC’97 Audio CODEC LSI, which is fully compliant with the industry standard “Audio
CODEC ’97” component specification (Revision 2.1).
Different from former AC’97, YMF743 supports new features like SPDIF OUT and Zoomed Video Port.
Without using a digital controller, these new features can be enhanced in the AC’97 sound system that has an
ICH controller built-in chipset.
Low power consumption is supported not only in the normal mode but can be controlled in the power-down
mode.
FEATURES
• AC’97 Revision 2.1 Compliant
• Exceeds PC98 / PC99 Audio Performance Requirements
• Analog Inputs :
- 4 Stereo Inputs: LINE, CD, VIDEO, AUX
- 2 Monaural Inputs: Speakerphone and PC BEEP Inputs
- 2 Independent Microphone Inputs
• PC BEEP can directly output to Line Out
• Internal +20dB amplifier circuitry for microphone
• Analog Outputs : Stereo LINE Output, True LINE Level and Monaural Output
• Supports Zoomed Video Port
• Supports Consumer IEC958 Output Port (SPDIF OUT)
• Supports 3D Enhancement (Wide Stereo), and Bass / Treble control
• Multiple CODEC Capability
• Programmable Power Down Mode
• Supports EAPD (External Amplifier Power Down)
• Power Supplies : Analog 5.0V, Digital 3.3V or 5.0V
• 48-Pin SQFP Package (YMF743-S)
YAMAHA CORPORATION
YMDF7e4c3eCmATbAeLO3G, 1998
CATALOG No.:LSI-4MF743A4
December 18, 2000






YMF743 Datasheet, Funktion
YMF743
MIXER REGISTERS
NAME
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
00h Reset
“0” “0” “0” “0” “0” “0” “0” “0” “0” “1” “0” “0” “0” “0” “0” “0” 0040h
02h Master vol. Mute -
ML5-0
--
MR5-0
8000h
04h LNLVL vol.
- - - - - - - - - - - - - - - - 0000h
06h Master vol. Mono Mute - - - - - - - - -
MM5-0
8000h
08h Master tone
-----
BA2-0
-----
TR2-0
0707h
0Ah PC_BEEP vol. Mute - - - - - - - - - -
PV3-0
- 0000h
0Ch Phone vol. Mute - - - - - - - - - -
GN4-0
8008h
0Eh Mic vol. Mute - - - - - - - - 20dB -
GN4-0
8008h
10h Line in vol. Mute - -
GL4-0
---
GR4-0
8808h
12h CD vol. Mute - -
GL4-0
---
GR4-0
8808h
14h Video vol. Mute - -
GL4-0
---
GR4-0
8808h
16h Aux vol. Mute - -
GL4-0
---
GR4-0
8808h
18h PCM out vol. Mute - -
GL4-0
---
GR4-0
8808h
1Ah Record Select
-----
SL2-0
-----
SR2-0
0000h
1Ch Record Gain Mute - - -
GL3-0
----
GR3-0
8000h
20h General Purpose POP - 3D - - - MIX MS LPBK - - - - - - - 0000h
22h 3D Control
----
WD3-1
- - - - - - - - - 0000h
26h Power Down EAPD - PR5 PR4 PR3 PR2 PR1 PR0 - - -
28h Extended Audio ID ID1 ID0 - - - - AMAP LDAC SDAC CDAC -
- REF ANL DAC ADC 000xh
- - - - - xxx0h
62h Vendor Function * * * * * * * * * * * * TX EXEN * * 0224h
64h ZV vol. Mute MSEL -
GL4-0
ZEN ZAC -
GR4-0
x848h
66h DIT Control C15 C14 C13 C12 C11 C10 C9 C8 C5 C4 C3 C2 C1 DMU UDS DEN 0000h
68h 3D Mode Select - - - - WM1-0 - - - - - - - - - - 0C00h
7Ch Vendor ID 1
“0” “1” “0” “1” “1” “0” “0” “1” “0” “1” “0” “0” “1” “1” “0” “1” 594Dh
7Eh Vendor ID 2
“0” “1” “0” “0” “1” “0” “0” “0” “0” “0” “0” “0” “0” “0” “0” “0” 4800h
Note) 62h except TX and EXEN bits should not be changed from the default value.
Do not access to 5Ah and 60h because they are LSI test registers.
00h : Reset (Read/Write reset, Default: 0040h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
“0” “0” “0” “0” “0” “0” “0” “0” “0” “1” “0” “0” “0” “0” “0” “0”
When any value is written to this register, all registers except for the lower 4 bits of 26h:Power Down are reset
to the default value.
6 December 18, 2000

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YMF743 pdf, datenblatt
YMF743
28h : Extended Audio ID (Read Only, Default: 0xxxh)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ID1 ID0 - - - - AMAP LDAC SDAC CDAC - - - - - -
ID1,ID0.........These bits indicate CODEC ID. The states is determined by setting both No.45 and 46 pins.
When MSEL is high, they are fixed to “Primary ID00”.
ID1# (No.46)
Pin Status Logic Value
ID0# (No.45)
Pin Status Logic Value
CODEC ID
Configuration
OPEN (“H”) “0” OPEN (“H”) “0” Primary ID00
OPEN (“H”)
“0”
GND (“L”)
“1” Secondary ID01
GND (“L”)
“1” OPEN (“H”) “0” Secondary ID10
GND (“L”) “1” GND (“L”) “1” Secondary ID11
AMAP...........This bit is hardwired to “1”. It indicates that the PCM DAC uses data of the standard slot into
twelve slots, as the following table.
CODEC
Slot Number
ID PCM Left DAC PCM Right DAC
00 3
4 Original definition (master)
01 3
4 Original definition (docking)
10 7
8 Left / Right surround channels
11 6
9 Center / LFE channels
LDAC ...........When PCM DAC uses the LFE channel, this bit is set to “1”.
SDAC ...........When PCM DAC uses the surround channels, this bit is set to “1”.
CDAC ...........When PCM DAC uses the center channel, this bit is set to “1”.
62h : Vendor Function (Read/Write, Default: 0224h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
* * * * * * * * * * * * TX EXEN *
TX.................This bit selects the pin function of No.47.
“0” : EAPD
“1” : DIT
EXEN ...........This bit selects whether EXT24M pin outputs clock or not.
“0” : EXT24M is power down state, and outputs low level.
“1” : EXT24M outputs clock.
The bits except TX and EXEN should not be changed from the default value.
D0
*
12 December 18, 2000

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