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PDF SC-601 Data sheet ( Hoja de datos )
| Número de pieza | SC-601 | |
| Descripción | Speech And Music Processor | |
| Fabricantes | Sensory | |
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SC-601
Speech And Music Processor
Data sheet
Features
Advanced, integrated speech synthesizer for
high-quality sound.
Operates up to 12.32 MHz (Performs up to 12
MIPS)
Single chip solution for up to 24 Minutes of
speech (using 1.57 Mb of onboard program +
data ROM)
Supports high-quality synthesis algorithms
Such as MX, CX, Simple CX, LX, ADPCM, and
Polyphonic Music
Simultaneous speech plus music capabilities
Very low-power operation, ideal for handheld
devices
Low-voltage operation, sustainable by three
batteries
Reduced power stand-by modes, less than 10
µA in deep-sleep mode
640-Word RAM
32 I/O Pins consisting of: 24 general purpose
bit configurable I/O, 8 inputs with programmable
pullup resistor and a dedicated interrupt (Key-
Scan)
Direct Speaker Driver, 32Ω (PDM)
One-bit comparator with edge-detection
interrupt service
Resistor-trimmed oscillator or 32.768kHz crystal
reference oscillator
Serial scan port for in-circuit emulation and
diagnostics
The SC-601 is sold in die form or 100-pin LQFP
package.
An emulator device is available in a ceramic
package for development (SC-614-P).
Description
The SC-601 is a low-cost, mixed-signal
processor that combines a speech synthesizer,
general-I/O, onboard ROM, and direct speaker
drive in a single package. The computational
16-Bit
Microprocessor
unit utilizes a powerful DSP which gives the SC-
601 unprecedented speed and computational
flexibility compared with previous devices of its
type. The SC-601 supports a variety of speech
and audio coding algorithms, providing range of
640-words
RAM
options for speech duration and sound quality.
The device consists of a micro-DSP core,
192 KBytes
ROM
embedded program, and data memory, and a
self-contained generation system. General-
purpose periphery is comprised of 32 bits of partially configurable I/O.
SC-601 Block Diagram
10-Bit
DAC
TIMER 1
TIMER 2
COMPARATOR
PLLM
32 I/O
The core processor is a general-purpose 16-bit microcontroller with DSP capability. The basic core includes
computational unit (CU), data address unit, program address unit, two timers, eight level interrupt processor,
and several system and control registers. The core processor gives the SC-601 break-capability in emulation.
The processor is Harvard type for efficient DSP algorithm execution. It requires separate program and memory
blocks to permit simultaneous access. The ROM has a protection scheme to prevent third-party pirating. It is
configured in 32K 17-bit words.
The total ROM space is divided into three areas:
1. The lower 2K words are reserved by Sensory a built-in self-test
2. The upper 30K words are for user program/data
3. An additional 1 Mb data ROM provides for up to 24 minutes of speech.
© 2002 Sensory Inc.
P/N 80-0207-A
1
1 page  
Data Sheet
SC-601
DC Electrical Characteristics, TA = 0 to 70°C
PARAMETER
TEST CONDITIONS
MIN TYP§ MAX UNIT
Positive going threshold
2.4
VDD = 3 V
Negative going threshold
1.8 V
RESET_ Threshold changes
Hysteresis
Positive going threshold
0.6
3.3
VDD = 5.2 V Negative going threshold
2.9 V
Hysteresis
0.4
VIH
VIL
IOH¶
IOL¶
IOH (DAC)
IOL (DAC)
High-level input voltage
VDD = 3 V
VDD = 4.5 V
VDD = 5.2 V
Low-level input voltage
VDD = 3 V
VDD = 4.5 V
VDD = 5.2 V
High-level output current per pin of I/O port
Low-level output current per pin of I/O port
High-level output DAC current
VDD = 4.5 V
Low-level output DAC current
VOH = 4 V
VOL = 0.5 V
VOH = 4 V
VOL = 0.5 V
23
3 4.5 V
3.5 5.2
01
0 1.5 V
0 1.7
–2 mA
5 mA
–10 mA
20 mA
Ilkg Input leakage current
Excludes OSCIN
1 µA
I(STANDBY)
IDD†
I(SLEEP-deep)
I(SLEEP-mid)
I(SLEEP-light)
VIO
Standby current
Operating current
Supply current
Input offset voltage
RESET is low
VDD = 4.5 V, FCLOCK = 12.32 MHz
VDD = 4.5 V, DAC off, ARM set, OSC disabled
VDD = 4.5 V, DAC off, ARM set, OSC enabled
VDD = 4.5 V, DAC off, ARM clear, OSC enabled
VDD = 4.5 V, Vref = 1 to 4.25 V
0.05 10 µA
15 mA
0.05 10
40 60 µA
60 100
25 50 mV
R(PULLUP) F port pullup resistance
VDD = 5 V
70 150
KΩ
∆f(RTO-trim) Trim deviation
RRTO = 470 KΩ, VDD = 4.5 V, TA = 25°C,
fRTO = 8.192 MHz (PLL setting = 7 Ch)‡
±1% ±3%
∆f(RTO-volt) Voltage deviation
RRTO = 470 KΩ, VDD = 3.5 to 5.2 V, TA = 25°C,
fRTO = 8.192 MHz (PLL setting = 7 Ch)‡
±1.5%
∆f(RTO-temp) Temperature deviation
RRTO = 470 KΩ, VDD = 4.5 V, TA = 0 to 70°C,
fRTO = 8.192 MHz (PLL setting = 7 Ch)‡
±0.03
%/°C
∆f(RTO-res) Resistance deviation
VDD = 4.5 V, TA = 25°C, R(OSC) = 470 KΩ at ±1%,
fRTO = 8.192 MHz (PLL setting = 7 Ch)‡
±1%
† Operating current assumes all inputs are tied to either VSS or VDD with no input currents due to programmed pullup resistors. The DAC
output and other outputs are open circuited.
‡ The best trim value is selected at nominal temperature and voltage but the deviation due to the trim error is ignored.
§ Typical voltage and current measurement taken at 25°C
¶ Cannot exceed 15 mA total per internal VDD pin. Port A, B share 1 internal VDD pin; Port C, D share 1 internal VDD
External Component Absolute Values
PARAMETER
R(RTO)
C(PLL)
RTO external resistance
PLL external capacitance
TEST CONDITIONS
TA = 25°C, 1% tolerance
TA = 25°C, 10% tolerance
MIN MAX UNIT
470 KΩ
3300
pF
© 2002 Sensory Inc.
P/N 80-0207-A
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet SC-601.PDF ] | |
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