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PDF HT46R48E Data sheet ( Hoja de datos )
| Número de pieza | HT46R48E | |
| Descripción | Cost-Effective A/D Type 8-Bit OTP MCU | |
| Fabricantes | Holtek Semiconductor | |
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HT46R48E
Cost-Effective A/D Type 8-Bit OTP MCU
Technical Document
· Tools Information
· FAQs
· Application Note
- HA0049E Read and Write Control of the HT1380
- HA0051E Li Battery Charger Demo Board - Using the HT46R47
- HA0052E Microcontroller Application - Battery Charger
- HA0083E Li Battery Charger Demo Board - Using the HT46R46
- HA0085E 8-bit Pseudo-Random Number Generator
Features
· Operating voltage:
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
· 19 bidirectional I/O lines (max.)
· 1 interrupt input shared with an I/O line
· 8-bit programmable timer/event counter with overflow
interrupt and 7-stage prescaler
· On-chip crystal and RC oscillator
· Watchdog Timer
· 2048´14 program memory
· 64´8 data memory RAM
· 128´8 data EEPROM
· Supports PFD for sound generation
· HALT function and wake-up feature reduce power
consumption
· Up to 0.5ms instruction cycle with 8MHz system clock
at VDD=5V
· 6-level subroutine nesting
· 4 channels 9-bit resolution A/D converter
· 1 channel 8-bit PWM output shared with an I/O line
· Bit manipulation instruction
· 14-bit table read instruction
· 63 powerful instructions
· All instructions in one or two machine cycles
· Low voltage reset function
· 24-pin SKDIP/SOP/SSOP package
General Description
The HT46R48E are 8-bit, high performance, RISC ar-
chitecture microcontroller devices specifically designed
for A/D applications that interface directly to analog sig-
nals, such as those from sensors.
There are two dice in the HT46R48E package: one is
the HT46R48 MCU, the other is a 128´8 bits EEPROM
used for data memory purpose. The two dice are
wire-bonded to form HT46R48E.
The advantages of low power consumption, I/O flexibil-
ity, programmable frequency divider, timer functions,
oscillator options, multi-channel A/D Converter, Pulse
Width Modulation function, HALT and wake-up func-
tions, enhance the versatility of these devices to suit a
wide range of A/D application possibilities such as sen-
sor signal processing, motor driving, industrial control,
consumer products, subsystem controllers, etc.
Rev. 1.10
1 March 24, 2006
1 page  
HT46R48E
EEPROM D.C. Characteristics
Symbol
Parameter
VCC
ICC1
ICC2
VIL
VIH
VOL
ILI
ILO
ISTB1
ISTB2
CIN
COUT
Operating Voltage
Operating Current
Operating Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Input Leakage Current
Output Leakage Current
Standby Current
Standby Current
Input Capacitance (See Note)
Output Capacitance (See Note)
Test Conditions
VCC Conditions
¾¾
5V Read at 100kHz
5V Write at 100kHz
¾¾
¾¾
2.4V
5V
5V
5V
2.4V
IOL=2.1mA
VIN=0 or VCC
VOUT=0 or VCC
VIN=0 or VCC
VIN=0 or VCC
¾ f=1MHz 25°C
¾ f=1MHz 25°C
Note: These parameters are periodically sampled but not 100% tested
VCC pad is wire-bonded to VDD pad of the HT46R48 die.
Min.
2.2
¾
¾
-1
0.7VCC
¾
¾
¾
¾
¾
¾
¾
Ta=25°C
Typ. Max. Unit
¾ 5.5
V
¾ 2 mA
¾ 5 mA
¾ 0.3VCC
V
¾ VCC+0.5 V
¾ 0.4
V
¾ 1 mA
¾ 1 mA
¾ 4 mA
¾ 3 mA
¾ 6 pF
¾ 8 pF
A.C. Characteristics
HT46R48
Symbol
Parameter
fSYS
System Clock
(Crystal OSC, RC OSC)
Test Conditions
VDD Conditions
¾ 2.2V~5.5V
¾ 3.3V~5.5V
fTIMER
Timer I/P Frequency
(TMR)
¾ 2.2V~5.5V
¾ 3.3V~5.5V
tWDTOSC Watchdog Oscillator Period
tWDT1
tWDT2
tRES
tSST
tLVR
tINT
tAD
tADC
tADCS
Watchdog Time-out Period
(RC OSC)
Watchdog Time-out Period
(System Clock)
External Reset Low Pulse Width
System Start-up Timer Period
Low Voltage Width to Reset
Interrupt Pulse Width
A/D Clock Period
A/D Conversion Time
A/D Sampling Time
3V ¾
5V ¾
¾¾
¾¾
¾¾
¾ Wake-up from HALT
¾¾
¾¾
¾¾
¾¾
¾¾
Min.
400
400
0
0
45
32
215
217
1
¾
0.25
1
1
¾
¾
Note: *tSYS=1/fSYS
Typ.
¾
¾
¾
¾
90
65
¾
¾
¾
1024
1
¾
¾
76
32
Ta=25°C
Max. Unit
4000
8000
4000
8000
180
130
kHz
kHz
kHz
kHz
ms
ms
216 tWDTOSC
218 tSYS
¾ ms
¾ *tSYS
2 ms
¾ ms
¾ ms
¾ tAD
¾ tAD
Rev. 1.10
5 March 24, 2006
5 Page 
HT46R48E
Bit No.
0
1
2
3
4
5
6
7
Label
EMI
EEI
ETI
EADI
EIF
TF
ADF
¾
Function
Controls the master (global) interrupt (1=enabled; 0=disabled)
Controls the external interrupt (1=enabled; 0=disabled)
Controls the Timer/Event Counter interrupt (1=enabled; 0=disabled)
Controls the A/D converter interrupt (1=enabled; 0=disabled)
External interrupt request flag (1=active; 0=inactive)
Internal Timer/Event Counter request flag (1=active; 0=inactive)
A/D converter request flag (1=active; 0=inactive)
For test mode used only.
Must be written as ²0²; otherwise may result in unpredictable operation.
INTC (0BH) Register
The A/D converter interrupt is initialized by setting the
A/D converter request flag (ADF; bit 6 of INTC), caused
by an end of A/D conversion. When the interrupt is en-
abled, the stack is not full and the ADF is set, a subrou-
tine call to location 0CH will occur. The related interrupt
request flag (ADF) will be reset and the EMI bit cleared
to disable further interrupts.
During the execution of an interrupt subroutine, other in-
terrupt acknowledgments are held until the RETI in-
struction is executed or the EMI bit and the related
interrupt control bit are set to 1 (of course, if the stack is
not full). To return from the interrupt subroutine, RET or
RETI may be invoked. RETI will set the EMI bit to enable
an interrupt service, but RET will not.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Interrupt Source
Priority
External Interrupt
1
Timer/Event Counter Overflow
2
A/D Converter Interrupt
3
Vector
04H
08H
0CH
The timer/event counter interrupt request flag (TF), ex-
ternal interrupt request flag (EIF), A/D converter request
flag (ADF), enable timer/event counter bit (ETI), enable
external interrupt bit (EEI), enable A/D converter inter-
rupt bit (EADI) and enable master interrupt bit (EMI)
constitute an interrupt control register (INTC) which is
located at 0BH in the data memory. EMI, EEI, ETI, EADI
are used to control the enabling/disabling of interrupts.
These bits prevent the requested interrupt from being
serviced. Once the interrupt request flags (TF, EIF, ADF)
are set, they will remain in the INTC register until the in-
terrupts are serviced or cleared by a software instruc-
tion.
It is recommended that a program does not use the
CALL subroutine within the interrupt subroutine. In-
terrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications.
If only one stack is left and enabling the interrupt is not
well controlled, the original control sequence will be dam-
aged once the ²CALL² operates in the interrupt subrou-
tine.
Oscillator Configuration
There are two oscillator circuits in the microcontroller.
O SC1
V DD
470pF
O SC1
O SC2
C r y s ta l O s c illa to r
fS Y S /4
O SC2
R C O s c illa to r
System Oscillator
Both are designed for system clocks, namely the RC os-
cillator and the Crystal oscillator, which are determined
by the options. No matter what oscillator type is se-
lected, the signal provides the system clock. The HALT
mode stops the system oscillator and ignores an exter-
nal signal to conserve power.
If an RC oscillator is used, an external resistor between
OSC1 and VSS is required and the resistance must
range from 24kW to 1MW. The system clock, divided by
4, is available on OSC2 with pull-high resistor, which
can be used to synchronize external logic. The RC os-
cillator provides the most cost effective solution. How-
ever, the frequency of oscillation may vary with VDD,
temperatures and the chip itself due to process varia-
tions. It is, therefore, not suitable for timing sensitive
operations where an accurate oscillator frequency is
desired.
Rev. 1.10
11 March 24, 2006
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HT46R48E.PDF ] | |
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