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AD12401 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD12401
Beschreibung 400 MSPS A/D Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 28 Seiten
AD12401 Datasheet, Funktion
www.DataSheet4U.com
FEATURES
Up to 400 MSPS sample rate
SNR of 63 dBFS @128 MHz
SFDR of 70 dBFS @128 MHz
VSWR of 1:1.5
High or low gain grades
Wideband ac-coupled input signal conditioning
Enhanced spurious-free dynamic range
Single-ended or differential ENCODE signal
LVDS output levels
Twos complement output data
APPLICATIONS
Communications test equipment
Radar and satellite subsystems
Phased array antennas, digital beams
Multichannel, multimode receivers
Secure communications
Wireless and wired broadband communications
Wideband carrier frequency systems
GENERAL DESCRIPTION
The AD12401 is a 12-bit analog-to-digital converter (ADC)
with a transformer-coupled analog input and digital post-
processing for enhanced SFDR. The product operates at up to
400 MSPS conversion rate with outstanding dynamic performance
in wideband carrier systems.
The AD12401 requires a 3.7 V analog supply and 3.3 V and
1.5 V digital supplies, and provides a flexible ENCODE signal
that can be differential or single ended. No external reference is
required.
The AD12401 package style is an enclosed 2.9" × 2.6" × 0.6"
module. Performance is rated over a 0°C to 60°C case
temperature range.
12-Bit, 400 MSPS A/D Converter
AD12401
FUNCTIONAL BLOCK DIAGRAM
AD12401
DATA
READY
A
ADC
A
DA0–DA11
POST-
CLK DISTRIBUTION PROCESSING
DB0–DB11
AIN
ADC
B
DR_EN
CLOCK DISTRIBUTION
DIVIDE BY 2
DATA
READY
B
ENC
ENC
OROUT
Figure 1.
PRODUCT HIGHLIGHTS
1. Guaranteed sample rate up to 400 MSPS.
2. Input signal conditioning with optimized dynamic
performance to 175 MHz.
3. High and low gain grades available.
4. Additional performance options available (sample rates
>400 MSPS or second Nyquist zone operation); contact
sales.
5. Proprietary Advanced Filter Bank (AFB™) digital post-
processing from V Corp Technologies, Inc.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.






AD12401 Datasheet, Funktion
www.DataSheet4U.com
AD12401
Parameter
SWITCHING SPECIFICATIONS
Conversion Rate6
Encode Pulse Width High (tEH)1
Encode Pulse Width Low (tEL)1
DIGITAL OUTPUT PARAMETERS
Valid Time (tV)
Propagation Delay (tPD)
Rise Time, tR (20% to 80%)
Fall Time, tF (20% to 80%)
DR Propagation Delay (tEDR)
Data to DR Skew (tEDR − tPD)
Pipeline Latency7
Start-Up Time
Postprocessing Configuration Time
APERTURE DELAY (tA)
APERTURE UNCERTAINTY (Jitter, tJ)
Case Temp
Full
60°C
60°C
Full
60°C
60°C
60°C
60°C
60°C
Full
Full
Full
60°C
60°C
Test Level
IV
V
V
IV
V
V
V
V
V
IV
IV
IV
V
V
AD12401-360KWS
Min Typ Max
356 360 364
1.38
1.38
4.5
8.7
0.3
0.3
11.5
2.8
74
29 44 87
3.1
2.3
0.4
Unit
MSPS
ns
ns
ns
ns
ns
ns
ns
ns
Cycles
ms
sec
ns
ps rms
1 All ac specifications tested with a single-ended, 2.0 V p-p encode on ENCODE and ENCODE floating.
2 The image spur is included in the SINAD specification.
3 The image spur is not included in the SFDR specification.
4 The image spur is at fS/2 – AIN; the offset spur is at fS/2.
5 F1 = 70 MHz, F2 = 73 MHz.
6 Parts are tested with 360 MSPS encode. Device can be clocked at lower encode rates, but specifications are not guaranteed. Specifications are guaranteed by design
for encode 360 MSPS ± 1%.
7 Pipeline latency is exactly 74 cycles with an additional tPD required for data to emerge.
AC SPECIFICATIONS1—ENCODE = 326 MSPS
VA = 3.7 V, VC = 3.3 V, VD = 1.5 V, ENCODE = 326 MSPS, 0°C ≤ TCASE ≤ 60°C, unless otherwise noted.
Table 4.
Parameter
DYNAMIC PERFORMANCE
SNR
Analog Input 10 MHz
@ −1.0 dBFS 70 MHz
128 MHz
SINAD2
Analog Input 10 MHz
@ −1.0 dBFS 70 MHz
128 MHz
Spurious-Free Dynamic Range3
Analog Input 10 MHz
@ −1.0 dBFS 70 MHz
128 MHz
Image Spur4
Analog Input 10 MHz
@ −1.0 dBFS 70 MHz
128 MHz
Offset Spur5
Analog Input @ −1.0 dBFS
Two-Tone IMD5
F1, F2 @ −6 dBFS
Case Temp
Test Level
AD12401-326KWS
AD12401-326JWS
Min Typ Max Min Typ Max
Full I
Full I
Full I
Full I
Full I
Full I
Full I
Full I
Full I
Full I
Full I
Full I
60°C V
60°C V
62 64
61.5 63.5
60 63
59 63.5
58.5 63
57.5 61.5
69 85
69 80
66 72
60 75
60 72
60 66
65
−75
60 62
59.5 61.5
58 61
57 61.5
56.5 61
55.5 59.5
69 85
69 80
66 72
60 75
60 72
60 66
65
−75
Unit
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
Rev. A | Page 6 of 28

6 Page









AD12401 pdf, datenblatt
www.DataSheet4U.com
AD12401
Pin No.
69
70
71
72
73
74
75
76
77
78
80
103
81 to 95, 109 to 112,
129 to 1321
113 to 120
121 to 1281
Mnemonic
DA3
DA2
DA3
DA2
DA1
DA0
DA1
DA0
DR_EN
DRA
DRA
H/L GAIN
AGND
VA
DGND
Description
Channel A Data Bit 3. Complement output bit.
Channel A Data Bit 2. Complement output bit.
Channel A Data Bit 3. True output bit.
Channel A Data Bit 2. True output bit.
Channel A Data Bit 1. Complement output bit.
Channel A Data Bit 0. Complement output bit. DA0 is LSB.
Channel A Data Bit 1. True output bit.
Channel A Data Bit 0. True output bit. DA0 is LSB.
Data Ready Enable, Typically DNC. See the DR_EN section.
Channel A Data Ready. Complement output.
Channel A Data Ready. True output.
Gain Select Pin. Ground for low gain mode (KWS); pull up to 3.3 V for high gain mode (JWS).
Analog Ground.
Analog Supply, 3.7 V.
Digital Ground.
1 Internal ground plane connections: Section A = DGND, Pin 121 to Pin 124; Section B = DGND, Pin 125 to Pin 128; Section C = AGND, Pin 129 to Pin 132.
Rev. A | Page 12 of 28

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