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PDF ISP1504C Data sheet ( Hoja de datos )
| Número de pieza | ISP1504C | |
| Descripción | ULPI Hi Speed USB Transceiver | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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ISP1504A; ISP1504C
ULPI Hi-Speed Universal Serial Bus On-The-Go transceiver
Rev. 01 — 19 October 2006
Product data sheet
1. General description
The ISP1504 is a Universal Serial Bus (USB) On-The-Go (OTG) transceiver that is fully
compliant with Universal Serial Bus Specification Rev. 2.0, On-The-Go Supplement to the
USB 2.0 Specification Rev. 1.2 and UTMI+ Low Pin Interface (ULPI) Specification
Rev. 1.1.
The ISP1504 can transmit and receive USB data at high-speed (480 Mbit/s), full-speed
(12 Mbit/s) and low-speed (1.5 Mbit/s), and provides a pin-optimized, physical layer
front-end attachment to USB host, peripheral and OTG devices.
It is ideal for use in portable electronic devices, such as mobile phones, digital still
cameras, digital video cameras, Personal Digital Assistants (PDAs) and digital audio
players. It allows USB Application-Specific Integrated Circuits (ASICs), Programmable
Logic Devices (PLDs) and any system chip set to interface with the physical layer of the
USB through a 12-pin interface.
The ISP1504 can interface to the link with digital I/O voltages in the range of
1.65 V to 3.6 V.
The ISP1504 is available in HVQFN32 package.
2. Features
I Fully complies with:
N Universal Serial Bus Specification Rev. 2.0
N On-The-Go Supplement to the USB 2.0 Specification Rev. 1.2
N UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1
I Interfaces to host, peripheral and OTG device cores; optimized for portable devices or
system ASICs with built-in USB OTG device core
I Complete Hi-Speed USB physical front-end solution that supports high-speed
(480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)
N Integrated 45 Ω ± 10 % high-speed termination resistors, 1.5 kΩ ± 5 % full-speed
device pull-up resistor, and 15 kΩ ± 5 % host termination resistors
N Integrated parallel-to-serial and serial-to-parallel converters to transmit and receive
N USB clock and data recovery to receive USB data at ±500 ppm
N Insertion of stuff bits during transmit and discarding of stuff bits during receive
N Non-Return-to-Zero Inverted (NRZI) encoding and decoding
N Supports bus reset, suspend, resume and high-speed detection handshake (chirp)
I Complete USB OTG physical front-end that supports Host Negotiation Protocol (HNP)
and Session Request Protocol (SRP)
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6. Pinning information
6.1 Pinning
ISP1504A; ISP1504C
ULPI HS USB OTG transceiver
terminal 1
index area
DATA0
VCC(I/O)
RREF
DM
DP
FAULT
ID
CPGND
1
2
3
4
5
6
7
8
ISP1504
24 DATA6
23 DATA7
22 VCC(I/O)
21 NXT
20 STP
19 DIR
18 REG1V8
17 RESET_N
Transparent top view
Fig 2. Pin configuration HVQFN32; top view
004aaa479
6.2 Pin description
Table 2. Pin description
Symbol[1][2]
Pin Type[3]
DATA0
1 I/O
VCC(I/O)
RREF
DM
DP
FAULT
2P
3 AI/O
4 AI/O
5 AI/O
6I
ID 7 I
CPGND
C_B
C_A
VCC
PSW_N
8P
9 AI/O
10 AI/O
11 P
12 OD
Description[4]
pin 0 of the bidirectional ULPI data bus
slew-rate controlled output (1 ns); plain input; programmable pull down
I/O supply rail
resistor reference
data minus (D−) pin of the USB cable
data plus (D+) pin of the USB cable
input pin for the external VBUS digital overcurrent or fault detector signal
plain input; 5 V tolerant
identification (ID) pin of the mini-USB cable
plain input; TTL level
charge pump ground
flying capacitor pin connection for the charge pump
flying capacitor pin connection for the charge pump
input supply voltage or battery source
active LOW external VBUS power switch or external charge pump enable
open-drain; 5 V tolerant
ISP1504A_ISP1504C_1
Product data sheet
Rev. 01 — 19 October 2006
© NXP B.V. 2006. All rights reserved.
5 of 84
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NXP Semiconductors
ISP1504A; ISP1504C
ULPI HS USB OTG transceiver
• CHIP_SELECT_N
• CLOCK
• DATA[7:0]
• DIR
• NXT
• RESET_N
• STP
If the ISP1504 CLOCK pin is configured as an input, the VCC(I/O) power must be provided
at the same time as the VCC power. If the VCC(I/O) power input is delayed with respect to
VCC, input clock mode stability cannot be guaranteed.
7.9.3 RREF
Resistor reference analog I/O pin. A resistor, RRREF, must be connected between RREF
and GND, as shown in Section 16. This provides an accurate voltage reference that
biases internal analog circuitry. Less accurate resistors cannot be used and will render the
ISP1504 unusable.
7.9.4 DP and DM
The DP (data plus) and DM (data minus) are USB differential data pins. These must be
connected to the D+ and D− pins of the USB receptacle.
7.9.5 FAULT
If an external VBUS overcurrent or fault circuit is used, the output fault indicator of that
circuit can be connected to the ISP1504 FAULT input pin. The ISP1504 will inform the link
of VBUS fault events by sending RXCMDs on the ULPI bus. To use the FAULT pin, the link
must:
• Set the USE_EXT_VBUS_IND register bit to logic 1.
• Set the polarity of the external fault signal using the IND_COMPL register bit.
• Set the IND_PASSTHRU register bit to logic 1.
If the FAULT pin is not used, it is recommended to connect to GND.
7.9.6 ID
For OTG implementations, the ID (identification) pin is connected to the ID pin of the
mini-USB receptacle. As defined in On-The-Go Supplement to the USB 2.0 Specification
Rev. 1.2, the ID pin dictates the initial role of the link. If ID is detected as HIGH, the link
must assume the role of a peripheral. If ID is detected as LOW, the link must assume a
host role. Roles can be swapped at a later time by using HNP.
If the ISP1504 is not used as an OTG PHY, but as a standard USB host or peripheral PHY,
the ID pin must be connected to ground.
7.9.7 CPGND
CPGND indicates the analog ground for the on-board charge pump. CPGND must always
be connected to ground, even when the charge pump is not used.
ISP1504A_ISP1504C_1
Product data sheet
Rev. 01 — 19 October 2006
© NXP B.V. 2006. All rights reserved.
11 of 84
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