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AD9252 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9252
Beschreibung 1.8 V ADC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9252 Datasheet, Funktion
Data Sheet
FEATURES
8 analog-to-digital converters (ADCs) integrated into 1 package
93.5 mW ADC power per channel at 50 MSPS
SNR = 73 dB (to Nyquist)
ENOB = 12 bits
SFDR = 84 dBc (to Nyquist)
Excellent linearity
DNL = ±0.4 LSB (typical); INL = ±1.5 LSB (typical)
Serial LVDS (ANSI-644, default)
Low power, reduced signal option (similar to IEEE 1596.3)
Data and frame clock outputs
325 MHz, full-power analog bandwidth
2 V p-p input voltage range
1.8 V supply operation
Serial port control
Full-chip and individual-channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Programmable clock and data alignment
Programmable output resolution
Standby mode
APPLICATIONS
Medical imaging and nondestructive ultrasound
Portable ultrasound and digital beam-forming systems
Quadrature radio receivers
Diversity radio receivers
Tape drives
Optical networking
Test equipment
GENERAL DESCRIPTION
The AD9252 is an octal, 14-bit, 50 MSPS ADC with an on-chip
sample-and-hold circuit designed for low cost, low power, small size,
and ease of use. Operating at a conversion rate of up to 50 MSPS,
it is optimized for outstanding dynamic performance and low
power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
The ADC automatically multiplies the sample rate clock for
the appropriate LVDS serial data rate. A data clock (DCO)
for capturing data on the output and a frame clock (FCO) for
signaling a new output byte are provided. Individual channel
power-down is supported and typically consumes less than
2 mW when all channels are disabled.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
Octal, 14-Bit, 50 MSPS,
Serial LVDS, 1.8 V ADC
AD9252
FUNCTIONAL BLOCK DIAGRAM
AVDD
PDWN
DRVDD DRGND
VIN + A
VIN – A
VIN + B
VIN – B
VIN + C
VIN – C
VIN + D
VIN – D
VIN + E
VIN – E
VIN + F
VIN – F
VIN + G
VIN – G
VIN + H
VIN – H
VREF
SENSE
REFT
REFB
AD9252
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
REF
SELECT
0.5V
SERIAL PORT
INTERFACE
14
SERIAL
LVDS
14
SERIAL
LVDS
14
SERIAL
LVDS
14
SERIAL
LVDS
14
SERIAL
LVDS
14
SERIAL
LVDS
14
SERIAL
LVDS
14
SERIAL
LVDS
DATA RATE
MULTIPLIER
D+A
D–A
D+B
D–B
D+C
D–C
D+D
D–D
D+E
D–E
D+F
D–F
D+G
D–G
D+H
D–H
FCO+
FCO–
DCO+
DCO–
RBIAS AGND CSB
SDIO/ SCLK/
ODM DTP
Figure 1.
CLK+
CLK–
The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom user-
defined test patterns entered via the serial port interface (SPI).
The AD9252 is available in an RoHS compliant, 64-lead LFCSP. It is
specified over the industrial temperature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
1. Small Footprint. Eight ADCs are contained in a small package.
2. Low Power of 93.5 mW per Channel at 50 MSPS.
3. Ease of Use. A data clock output (DCO) operates up to
350 MHz and supports double data rate (DDR) operation.
4. User Flexibility. SPI control offers a wide range of flexible
features to meet specific system requirements.
5. Pin-Compatible Family. This includes the AD9212 (10-bit)
and AD9222 (12-bit).
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006–2011 Analog Devices, Inc. All rights reserved.






AD9252 Datasheet, Funktion
Data Sheet
AD9252
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 3.
Parameter1
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Differential Input Voltage2
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
LOGIC INPUTS (PDWN, SCLK/DTP)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (CSB)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (SDIO/ODM)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC OUTPUT (SDIO/ODM)3
Logic 1 Voltage (IOH = 800 μA)
Logic 0 Voltage (IOL = 50 μA)
DIGITAL OUTPUTS (D + x, D − x), (ANSI-644)
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
DIGITAL OUTPUTS (D + x, D − x),
(LOW POWER, REDUCED SIGNAL OPTION)
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
Temperature
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
Full
Full
Full
Full
Min
250
1.2
1.2
1.2
0
247
1.125
150
1.10
AD9252-50
Typ
Max
CMOS/LVDS/LVPECL
1.2
20
1.5
3.6
0.3
30
0.5
3.6
0.3
70
0.5
DRVDD + 0.3
0.3
30
2
1.79
0.05
LVDS
Offset binary
454
1.375
LVDS
Offset binary
250
1.30
Unit
mV p-p
V
kΩ
pF
V
V
kΩ
pF
V
V
kΩ
pF
V
V
kΩ
pF
V
V
mV
V
mV
V
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2 This is specified for LVDS and LVPECL only.
3 This is specified for 13 SDIO pins sharing the same connection.
Rev. E | Page 5 of 52

6 Page









AD9252 pdf, datenblatt
Data Sheet
Pin No.
32
33
34
38
39
40
41
43
44
46
47
49
50
52
53
54
55
56
57
58
60
61
63
64
Mnemonic
D+B
D−A
D+A
SCLK/DTP
SDIO/ODM
CSB
PDWN
VIN + A
VIN − A
VIN − B
VIN + B
VIN + C
VIN − C
VIN − D
VIN + D
RBIAS
SENSE
VREF
REFB
REFT
VIN + E
VIN − E
VIN − F
VIN + F
Description
ADC B Digital Output True
ADC A Digital Output Complement
ADC A Digital Output True
Serial Clock/Digital Test Pattern
Serial Data Input-Output/Output Driver Mode
Chip Select Bar
Power-Down
ADC A Analog Input True
ADC A Analog Input Complement
ADC B Analog Input Complement
ADC B Analog Input True
ADC C Analog Input True
ADC C Analog Input Complement
ADC D Analog Input Complement
ADC D Analog Input True
External Resistor to Set the Internal ADC Core Bias Current
Reference Mode Selection
Voltage Reference Input/Output
Negative Differential Reference
Positive Differential Reference
ADC E Analog Input True
ADC E Analog Input Complement
ADC F Analog Input Complement
ADC F Analog Input True
AD9252
Rev. E | Page 11 of 52

12 Page





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