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ADV7322 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADV7322
Beschreibung Multiformat 11-Bit HDTV Video Encoder
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADV7322 Datasheet, Funktion
www.DataSheet4U.com
Preliminary Technical Data
FEATURES
High definition input formats
16-, 24-bit (4:2:2, 4:4:4) parallel YCrCb
Fully compliant with
SMPTE 274M (1080i, 1080p @ 74.25 MHz)
SMPTE 296M (720p)
SMPTE 240M (1035i)
RGB in 3- × 8-bit 4:4:4 input format
HDTV RGB supported
RGB, RGBHV
Other high definition formats using async
timing mode
Enhanced definition input formats
8-, 16-, 24-bit (4:2:2, 4:4:4) parallel YCrCb
SMPTE 293M (525p)
BTA T-1004 EDTV2 (525p)
ITU-R BT.1358 (625p/525p)
ITU-R BT.1362 (625p/525p)
RGB in 3- × 8-bit 4:4:4 input format
Standard definition input formats
CCIR-656 4:2:2 8-bit or 16-bit parallel input
High definition output formats
YPrPb HDTV (EIA 770.3)
RGB, RGBHV
CGMS-A (720p/1080i)
Enhanced definition output formats
Macrovision Rev 1.2 (525p/625p)
CGMS-A (525p/625p)
YPrPb progressive scan (EIA-770.1, EIA-770.2)
RGB, RGBHV
Standard definition output formats
Composite NTSC M/N
Composite PAL M/N/B/D/G/H/I, PAL-60
SMPTE 170M NTSC-compatible composite video
ITU-R BT.470 PAL-compatible composite video
S-video (Y/C)
EuroScart RGB
Component YPrPb (Betacam, MII, SMPTE/EBU N10)
Macrovision Rev 7.1.L1
CGMS/WSS
Closed captioning
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Multiformat 11-Bit
HDTV Video Encoder
ADV7322
GENERAL FEATURES
Simultaneous SD/HD, PS/SD inputs and outputs
Oversampling up to 216 MHz
Programmable DAC gain control
Sync outputs in all modes
On-board voltage reference
Six 11-bit precision video DACs
2-wire serial I2C® interface, open-drain configuration
Dual I/O supply 2.5 V/3.3 V operation
Analog and digital supply 2.5 V
On-board PLL
64-lead LQFP package
Lead (Pb)-free product
APPLICATIONS
EVD players (enhanced versatile disk)
SD/PS DVD recorders/players
SD/progressive scan/HDTV display devices
SD/HDTV set top boxes
Y7–Y0
C7–C0
S7–S0
HSYNC
VSYNC
BLANK
CLKIN_A
CLKIN_B
STANDARD DEFINITION
CONTROL BLOCK
COLOR CONTROL
BRIGHTNESS
DNR
GAMMA
PROGRAMMABLE
FILTERS
SD TEST PATTERN
D
E PROGRAMMABLE
M RGB MATRIX
U
X
TIMING
GENERATOR
HIGH DEFINITION
CONTROL BLOCK
HD TEST PATTERN
COLOR CONTROL
ADAPTIVE FILTER CTRL
SHARPNESS FILTER
PLL
ADV7322
11-BIT
DAC
O 11-BIT
V DAC
E
R
S
A
11-BIT
DAC
M
P 11-BIT
L DAC
I
N
G
11-BIT
DAC
11-BIT
DAC
I2C
INTERFACE
Figure 1. Simplified Functional Block Diagram
GENERAL DESCRIPTION
The ADV®7322 is a high speed, digital-to-analog encoder on a
single monolithic chip. It includes six high speed video DACs
with TTL compatible inputs. It has separate 8-, 16-, 24-bit input
ports that accept data in high definition and/or standard
definition video format. For all standards, external horizontal,
vertical, and blanking signals or EAV/SAV timing codes control
the insertion of appropriate synchronization signals into the
digital data stream and therefore the output signal.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.






ADV7322 Datasheet, Funktion
www.DataSheet4U.com
ADV7322
Preliminary Technical Data
SPECIFICATIONS
VAA = 2.375 V − 2.625 V, VDD = 2.375 V − 2.625 V, VDD_IO = 2.375 V − 3.6 V, VREF = 1.235 V, RSET = 3040 Ω, RLOAD = 300 Ω. All specifications
TMIN to TMAX (0°C to 70°C), unless otherwise noted.
Table 2.
Parameter
STATIC PERFORMANCE1
Resolution
Integral Nonlinearity
Differential Nonlinearity2, +ve
Differential Nonlinearity2, −ve
DIGITAL OUTPUTS
Output Low Voltage, VOL
Output High Voltage, VOH
Three-State Leakage Current
Three-State Output Capacitance
DIGITAL AND CONTROL INPUTS
Input High Voltage, VIH
Input Low Voltage, VIL
Input Leakage Current
Input Capacitance, CIN
ANALOG OUTPUTS
Full-Scale Output Current
Output Current Range
DAC to DAC Matching
Output Compliance Range, VOC
Output Capacitance, COUT
VOLTAGE REFERENCE
Internal Reference Range, VREF
External Reference Range, VREF
VREF Current4
POWER REQUIREMENTS
Normal Power Mode
IDD5
IDD_IO
IAA7, 8
Sleep Mode
IDD
IAA
IDD_IO
POWER SUPPLY REJECTION RATIO
Min
2.4[2.0]3
2
4.1
4.1
0
1.15
1.15
Typ Max
11
1.5
0.5
1.0
0.4 [0.4]3
±1.0
2
10
2
4.33
4.33
1.0
1.0
7
1.235
1.235
±10
0.8
4.6
4.6
1.4
1.3
1.3
Unit
Bits
LSB
LSB
LSB
V
V
µA
pF
V
V
µA
pF
mA
mA
%
V
pF
V
V
µA
Test Conditions
ISINK = 3.2 mA
ISOURCE = 400 µA
VIN = 0.4 V, 2.4 V
VIN = 2.4 V
137
78
73
140 1906
1.0
37 45
80
7
250
0.01
mA SD only [16×]
mA PS only [8×]
mA HDTV only [2×]
mA SD[16×, 8 bit] + PS[8×, 16 bit]
mA
mA
µA
µA
µA
%/%
1Oversampling disabled. Static DAC performance will be improved with increased oversampling ratios.
2DNL measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal step value; for −ve DNL, the
actual step value lies below the ideal step value.
3Value in brackets for VDD_IO = 2.375 V − 2.75 V.
4External current required to overdrive internal VREF.
5IDD, the circuit current, is the continuous current required to drive the digital core.
6Guaranteed maximum by characterization.
7All DACs on.
8IAA is the total current required to supply all DACs including the VREF circuitry and the PLL circuitry.
Rev. PrA | Page 6 of 88

6 Page









ADV7322 pdf, datenblatt
www.DataSheet4U.com
ADV7322
Preliminary Technical Data
CLKIN_A
t9 t10
Y7–Y0 FF 00 00 XY Cb0 Y0 Cr0
CONTROL
OUTPUTS
t12
t11
t13
t14
t9 = CLOCK HIGH TIME
t10 = CLOCK LOW TIME
t11 = DATA SETUP TIME
t12 = DATA HOLD TIME
NOTE: Y0, Cb0 SEQUENCE AS PER SUBADDRESS 0x01 BIT-1
Figure 9. PS Only 4:2:2 8-Bit Interleaved at 54 MHz EAV/SAV Input Mode [Input Mode 111]
Y1
CLKIN_B
CONTROL
INPUTS
P_HSYNC,
P_VSYNC,
P_BLANK
Y7–Y0
C7–C0
t9 t10
t12
Y0 Y1 Y2 Y3 Y4 Y5
Cb0 Cr0 Cb2 Cr2 Cb4 Cr4
t11
HD INPUT
CLKIN_A
CONTROL
INPUTS
S_HSYNC,
S_VSYNC,
S_BLANK
t9 t10
t12
SD INPUT
S7–S0
Cb0 Y0 Cr0
Y1 Cb1 Y2
t11
Figure 10. HD 4:2:2 and SD (8-Bit) Simultaneous Input Mode [Input Mode 101: SD Oversampled] [Input Mode 110: HD Oversampled]
Rev. PrA | Page 12 of 88

12 Page





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