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TJA1021 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer TJA1021
Beschreibung Transceiver
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 22 Seiten
TJA1021 Datasheet, Funktion
www.DataSheet4U.com
TJA1021
LIN 2.0/SAE J2602 transceiver
Rev. 01 — 16 October 2006
Objective data sheet
1. General description
The TJA1021 is the interface between the Local Interconnect Network (LIN) master/slave
protocol controller and the physical bus in a LIN. It is primarily intended for in-vehicle
sub-networks using baud rates from 1 kBd up to 20 kBd and is LIN 2.0/SAE J2602
compliant. The TJA1021 is pin-to-pin compatible with the TJA1020 and improved on
ElectroStatic Discharge (ESD).
The transmit data stream of the protocol controller at the transmit data input (TXD) is
converted by the TJA1021 into a bus signal with optimized slew rate and wave shaping to
minimize ElectroMagnetic Emission (EME). The LIN bus output pin is pulled HIGH via an
internal termination resistor. For a master application an external resistor in series with a
diode should be connected between pin INH or pin VBAT and pin LIN. The receiver detects
the data stream at the LIN bus input pin and transfers it via pin RXD to the microcontroller.
In sleep mode the power consumption of the TJA1021 is very low, whereas in failure
modes the power consumption is reduced to a minimum.
2. Features
2.1 General
I LIN 2.0/SAE J2602 compliant
I Baud rate up to 20 kBd
I Very low ElectroMagnetic Emission (EME)
I High ElectroMagnetic Immunity (EMI)
I Passive behavior in unpowered state
I Input levels compatible with 3.3 V and 5 V devices
I Integrated termination resistor for LIN slave applications
I Wake-up source recognition (local or remote)
I Supports K-line like functions
I Pin-to-pin compatible with TJA1020
2.2 Low power management
I Very low current consumption in sleep mode with local and remote wake-up
2.3 Protections
I High ESD robustness: ≥ ±6 kV according to IEC 61000-4-2 for pins LIN, VBAT and
WAKE_N
I Transmit data (TXD) dominant time-out function
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TJA1021 Datasheet, Funktion
www.DataSheet4U.com
NXP Semiconductors
TJA1021
LIN 2.0/SAE J2602 transceiver
[1] The standby mode is entered automatically upon any local or remote wake-up event during sleep mode. Pin INH and the 30 k
termination resistor at pin LIN are switched on.
[2] The internal wake-up source flag (set if a local wake-up did occur and fed to pin TXD) will be reset when entering normal mode (SLP_N
goes HIGH).
[3] The wake-up interrupt (on pin RXD) is released when entering normal mode (SLP_N goes HIGH).
[4] The normal mode is entered during a positive edge on SLP_N. As long as TXD is LOW, the transmitter is off. In the event of a
short-circuit to ground on pin TXD, the transmitter will be disabled.
[5] The power-on mode is entered after switching on VBAT.
7.2 Sleep mode
This mode is the most power saving mode of the TJA1021. Despite its extreme low
current consumption, the TJA1021 can still be waken up remotely via pin LIN, or waken up
locally via pin WAKE_N, or activated directly via pin SLP_N. Filters at the inputs of the
receiver (LIN), of pin WAKE_N and of pin SLP_N are preventing unwanted wake-up
events due to automotive transients or EMI. All wake-up events have to be maintained for
a certain time period (tdom(LIN), twake(dom)WAKE_N and tgotonorm).
The sleep mode is initiated by a falling edge on the pin SLP_N in normal mode. To enter
the sleep mode successfully (INH becomes floating), the sleep command (pin
SLP_N = LOW) must be maintained for at least tgotosleep.
In sleep mode the internal slave termination between pins LIN and VBAT is disabled to
minimize the power dissipation in case pin LIN is short-circuited to ground. Only a weak
pull-up between pins LIN and VBAT is present.
The sleep mode can be activated independently from the actual level on pin LIN, pin TXD
or pin WAKE_N. So it is guaranteed that the lowest power consumption is achievable even
in case of a continuous dominant level on pin LIN or a continuous LOW on pin WAKE_N.
When VBAT drops below the power-on-reset threshold Vth(POR)L, the TJA1021 enters sleep
mode.
7.3 Standby mode
The standby mode is entered automatically whenever a local or remote wake-up occurs
while the TJA1021 is in its sleep mode. These wake-up events activate pin INH and
enable the slave termination resistor at the pin LIN. As a result of the HIGH condition on
pin INH the voltage regulator and the microcontroller can be activated.
The standby mode is signalled by a LOW-level on pin RXD which can be used as an
interrupt for the microcontroller.
In the standby mode (pin SLP_N is still LOW), the condition of pin TXD (weak pull-down or
strong pull-down) indicates the wake-up source: weak pull-down for a remote wake-up
request and strong pull-down for a local wake-up request.
Setting pin SLP_N HIGH during standby mode results in the following events:
An immediate reset of the wake-up source flag; thus releasing the possible strong
pull-down at pin TXD before the actual mode change (after tgotonorm) is performed
A change into normal mode if the HIGH level on pin SLP_N has been maintained for a
certain time period (tgotonorm) while pin TXD is pulled HIGH
An immediate reset of the wake-up request signal on pin RXD
TJA1021_1
Objective data sheet
Rev. 01 — 16 October 2006
© NXP B.V. 2006. All rights reserved.
6 of 22
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TJA1021 pdf, datenblatt
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NXP Semiconductors
TJA1021
LIN 2.0/SAE J2602 transceiver
Table 8. Static characteristics …continued
VBAT = 5.5 V to 27 V; Tvj = 40 °C to +150 °C; RL(LIN-VBAT) = 500 ; all voltages are defined with respect to ground; positive
currents flow into the IC; typical values are given at VBAT = 12 V; unless otherwise specified.[1]
Symbol
Parameter
Conditions
Min
Typ Max
Unit
Pin TXD
VIH
VIL
Vhys
RPD(TXD)
HIGH-level input voltage
LOW-level input voltage
hysteresis voltage
pull-down resistance on VTXD = 5 V
pin TXD
2 -7 V
0.3 - +0.8 V
50
150 350
mV
150 350 650 k
IIL
IOL
Pin SLP_N
LOW-level input current VTXD = 0 V
LOW-level output current local wake-up request;
standby mode;
VWAKE_N = 0 V;
VLIN = VBAT;
VTXD = 0.4 V
5
1.5
- +5
--
µA
mA
VIH
VIL
Vhys
RPD(SLP_N)
HIGH-level input voltage
LOW-level input voltage
hysteresis voltage
pull-down resistance on VSLP_N = 5 V
pin SLP_N
2 -7 V
0.3 - +0.8 V
0.15 - 0.5
V
150 350 650 k
IIL LOW-level input current VSLP_N = 0 V
Pin RXD (open-drain)
5 0 +5 µA
IOL
ILH
Pin WAKE_N
LOW-level output current normal mode;
VLIN = 0 V;
VRXD = 0.4 V
HIGH-level leakage
current
normal mode;
VLIN = VBAT; VRXD = 5 V
1.5
5
--
0 +5
mA
µA
VIH
VIL
Ipu(L)
HIGH-level input voltage
LOW-level input voltage
LOW-level pull-up
current
VWAKE_N = 0 V
VBAT 1
<tbd>
30
- VBAT + 0.3 V
- VBAT 3.3 V
12 1
µA
ILH
Pin INH
HIGH-level leakage
current
VWAKE_N = 27 V;
VBAT = 27 V
5 0 +5 µA
Rsw(VBAT-INH)
ILH
Pin LIN
switch-on resistance
between pins VBAT and
INH
HIGH-level leakage
current
standby; normal mode;
power-on mode;
IINH = 15 mA;
VBAT = 12 V
sleep mode;
VINH = 27 V;
VBAT = 27 V
-
5
20 50
0 +5
µA
IBUS_LIM
Rpu
current limitation for
driver dominant state
pull-up resistance
VBAT = 18 V;
VLIN = 18 V; VTXD = 0 V
40
50
- 100
160 250
mA
k
TJA1021_1
Objective data sheet
Rev. 01 — 16 October 2006
© NXP B.V. 2006. All rights reserved.
12 of 22
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