|
|
PDF MB15F02SL Data sheet ( Hoja de datos )
| Número de pieza | MB15F02SL | |
| Descripción | Dual Serial Input PLL Frequency Synthesizer | |
| Fabricantes | Fujitsu Media Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MB15F02SL (archivo pdf) en la parte inferior de esta página. Total 25 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
FUJITSU SEMICONDUCTOR
DATA SHEET
ASSP
Dual Serial Input
PLL Frequency Synthesizer
MB15F02SL
DS04-21356-3E
s DESCRIPTION
The Fujitsu MB15F02SL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 1200 MHz and a
500 MHz prescalers. The 1200 MHz and 500 MHz prescalers have a dual modulus division ratio of 128/129 or
64/65, and a 8/9 or a 16/17 enabling pulse swallowing operation.
The supply voltage range is between 2.4 V and 3.6 V. The MB15F02SL uses the latest BiCMOS process. As a result,
the supply current is typically 3 mA at 2.7 V. A refined charge pump supplies a well-balanced output current of 1.5
mA or 6 mA. The charge pump current is selectable by serial data.
MB15F02SL is ideally suited for wireless mobile communications, such as GSM and PDC.
s FEATURES
• High frequency operation: RF synthesizer: 1200 MHz max
IF synthesizer: 500 MHz max
• Low power supply voltage: VCC = 2.4 to 3.6 V
• Ultra Low power supply current: ICC = 3.0 mA typ. (VCC = 2.7 V, Ta = +25°C, in IF, RF locking state)
ICC = 3.5 mA typ. (VCC = 3.0 V, Ta = +25°C, in IF, RF locking state)
• Direct power saving function: Power supply current in power saving mode
Typ. 0.1 µA (VCC = 3.0 V, Ta = +25°C), Max. 10 µA (VCC = 3.0 V)
• Dual modulus prescaler: 1200 MHz prescaler (64/65, 128/129)/500 MHz prescaler (8/9 or 16/17)
• Serial input 14-bit programmable reference divider: R = 3 to 16,383
• Serial input programmable divider consisting of:
- Binary 7-bit swallow counter: 0 to 127
- Binary 11-bit programmable counter: 3 to 2,047
• Software selectable charge pump current
• On-chip phase control for phase comparator
• Operating temperature: Ta = –40 to +85°C
• Pin compatible with MB15F02, MB15F02L
s PACKAGES
16-pin plastic SSOP
16-pad plastic BCC
(FPT-16P-M05)
(LCC-16P-M04)
1 page  
www.DataSheet4U.com
MB15F02SL
s ABSOLUTE MAXIMUM RATINGS
Parameter
Power supply voltage
Input voltage
Output voltage
Storage temperature
Symbol
VCC
VI
VO
Tstg
Rating
Min.
Max.
–0.5
+4.0
–0.5
VCC +0.5
GND
VCC
–55 +125
Unit
V
V
V
°C
Remark
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min.
Value
Typ.
Max.
Unit
Remark
Power supply voltage
VCC 2.4 3.0 3.6 V
Input voltage
VI
GND
–
VCC V
Operating temperature
Ta –40 – +85 °C
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
5
5 Page 
www.DataSheet4U.com
MB15F02SL
Table 9. Charge Pump Current Setting
CS Current value
H ±6.0 mA
L ±1.5 mA
Power Saving Mode (Intermittent Mode Control Circuit)
Table 10. PS Pin Setting
PS pin
H
L
Status
Normal mode
Power saving mode
The intermittent mode control circuit reduces the PLL power consumption.
By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See
the Electrical Characteristics chart for the specific value.
The phase detector output, Do, becomes high impedance.
For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table.
Setting the PS pin high, releases the power saving mode, and the device works normally.
The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation.
When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is because
of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can
cause a major change in the comparator output, resulting in a VCO frequency jump and an increase in lockup time.
To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error signal
from the phase detector when it returns to normal operation.
Note: • When power (VCC) is first applied, the device must be in standby mode, PS = Low, for at least 1 µs.
• PS pin must be set at “L” for Power-ON.
OFF
ON
VCC tv ≥ 1 µs
Clock
Data
,,,,,,,,,,,,,,
LE
tps ≥ 100 ns
PS
(1) (2) (3)
(1) PS = “L” (power saving mode) at Power-ON
(2) Set serial data 1 µs later after power supply remains stable (VCC > 2.2 V).
(3) Release power saving mode (PS: “L” → “H”) 100 ns later after setting serial data.
11
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet MB15F02SL.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MB15F02SL | Dual Serial Input PLL Frequency Synthesizer | Fujitsu Media Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |