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PDF CY7C63101C Data sheet ( Hoja de datos )
| Número de pieza | CY7C63101C | |
| Descripción | (CY7C63001C / CY7C63101C) Universal Serial Bun Microcontroller | |
| Fabricantes | Cypress | |
| Logotipo |  |
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CY7C63001C
CY7C63101C
Universal Serial Bus Microcontroller
1.0 Features
• Low-cost solution for low-speed USB peripherals such
as mouse, joystick, and gamepad
• USB Specification Compliance
— Conforms to USB 1.5 Mbps Specification, Version 1.1
— Supports 1 device address and 2 endpoints (1
control endpoint and 1 data endpoint)
• 8-bit RISC microcontroller
— Harvard architecture
— 6-MHz external ceramic resonator
— 12-MHz internal operation
— USB optimized instruction set
• Internal memory
— 128 bytes of RAM
— 4 Kbytes of EPROM
— Integrated USB transceiver
— Up to 16 Schmitt trigger I/O pins with internal pull-up
— Up to 8 I/O pins with LED drive capability
— Special purpose I/O mode supports optimization of
photo transistor and LED in mouse application
— Maskable Interrupts on all I/O pins
• 8-bit free-running timer
• Watch dog timer (WDT)
• Internal power-on reset (POR)
• Instant-On Now™ for Suspend and Periodic Wake-up
Modes
• Improved output drivers to reduce EMI
• Operating voltage from 4.0V to 5.25 VDC
• Operating temperature from 0 to 70 degree Celsius
• Available in space saving and low cost 20-pin PDIP,
20-pin SOIC, and 24-pin QSOP packages
• Industry standard programmer support
Logic Block Diagram
6-MHz
CERAMIC RESONATOR R/CEXT
OSC
INSTANT-ON
NOW™
RAM
128-Byte
8-bit
Timer
EPROM
2/4 KByte
Power-
on Reset
Watch
Dog
Timer
8-bit
RISC
core
Interrupt
Controller
USB
Engine
PORT
0
PORT
1
D+,D–
VCC/VSS
P0.0–P0.7
P1.0–P1.7
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-08026 Rev. *B
Revised November 28, 2005
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CY7C63001C
CY7C63101C
6.1.3 Data Memory Organization
The USB Controller includes 128 bytes of data RAM. The
upper 16 bytes of the data memory are used as USB FIFOs
for Endpoint 0 and Endpoint 1. Each endpoint is associated
with an 8-byte FIFO.
The USB controller includes two pointers into data RAM, the
Program Stack Pointer (PSP) and the Data Stack Pointer
(DSP). The value of PSP after reset is 0x00. The PSP incre-
ments by 2 whenever a CALL instruction is executed and it
decrements by 2 whenever a RET instruction is used.
after reset
DSP
PSP
The DSP pre-decrements by 1 whenever a PUSH instruction
is executed and it increments by 1 after a POP instruction is
used. The default value of the DSP after reset is 0x00, which
would cause the first PUSH to write into USB FIFO space for
Endpoint 1. Therefore, the DSP should be mapped to a
location such as 0x70 before initiating any data stack opera-
tions. Refer to the Reset section for more information about
DSP remapping after reset. Figure 6-2 illustrates the Data
Memory Space.
Address
0x00
0x02
user
firmware
0x04
DSP
0x70
USB FIFO - Endpoint 0
0x77
0x78
USB FIFO - Endpoint 1
0x7F
Figure 6-2. Data Memory Space
Document #: 38-08026 Rev. *B
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CY7C63001C
CY7C63101C
XTALOUT
clk1x
(to USB SIE)
clk2x
(to Microcontroller)
Clock
Doubler
30 pF
30 pF
XTALIN
Figure 2. Clock Oscillator On-chip Circuit
6.7 XTALIN/XTALOUT
The XTALIN and XTALOUT pins support connection of a
6-MHz ceramic resonator. The feedback capacitors and bias
resistor are internal to the IC, as shown in Figure 2 Leave
XTALOUT unconnected when driving XTALIN from an external
oscillator.
6.8 Interrupts
The interrupt controller contains a separate latch for each
interrupt. See Figure 3 for the logic block diagram for the
interrupt controller. When an interrupt is generated, it is
latched as a pending interrupt. It stays as a pending interrupt
until it is serviced or a reset occurs. A pending interrupt only
generates an interrupt request if it is enabled in the Global
Interrupt Enable Register. The highest priority interrupt
request is serviced following the execution of the current
instruction.
Interrupts are generated by the General Purpose I/O lines, the
Cext pin, the internal timer, and the USB engine. All interrupts
are maskable by the Global Interrupt Enable Register. Access
to this register is accomplished via IORD, IOWR, and IOWX
instructions to address 0x20. Writing a “1” to a bit position
enables the interrupt associated with that position. During a
reset, the contents of the Interrupt Enable Register are
cleared, disabling all interrupts. Figure 6-13 illustrates the
format of the Global Interrupt Enable Register.
When servicing an interrupt, the hardware first disables all
interrupts by clearing the Global Interrupt Enable Register.
Next, the interrupt latch of the current interrupt is cleared. This
is followed by a CALL instruction to the ROM address
associated with the interrupt being serviced (i.e., the interrupt
vector). The instruction in the interrupt table is typically a JMP
instruction to the address of the Interrupt Service Routine
(ISR). The user can re-enable interrupts in the interrupt service
routine by writing to the appropriate bits in the Global Interrupt
Enable Register. Interrupts can be nested to a level limited
only by the available stack space.
b7 b6 b5 b4 b3 b2 b1 b0
CEXTIE
GPIOIE
Reserved
EP1IE
EP0IE
1024IE
128IE
Reserved
R/W R/W
R/W R/W R/W R/W
00000000
Figure 6-13. Global Interrupt Enable Register (GIER - Address 0x20)
Global
Interrupt
Enable
Register
CLR
Interrupt
Acknowledge
Logic 1
128-µs
Interrupt
CLR
DQ
CLK
Enable [1]
Enable [7:0]
Logic 1
GPIO
Interrupt
CLR
DQ
CLK
Enable [6]
128-µs CLR
128-µs IRQ
1-ms CLR
1-ms IRQ
End P0 CLR
End P0 IRQ
End P1 CLR
End P1 IRQ
GPIO CLR
GPIO IRQ
IRQ
Interrupt
Vector
CLR
Logic 1 D
Q Enable [7]
CEXT
CLK
Wake-up CLR
Wake-up IRQ
Interrupt
Priority
Encoder
Figure 3. Interrupt Controller Logic Block Diagram
Document #: 38-08026 Rev. *B
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