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PDF MC145422 Data sheet ( Hoja de datos )
| Número de pieza | MC145422 | |
| Descripción | (MC145422 / MC145426) UNIVERSAL DIGITAL-LOOP TRANSCEIVER(UDLT) | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Universal Digital-Loop
Transceivers (UDLT)
The MC145422 and MC145426 UDLTs are high–speed data transceivers
that provide 80 kbps full–duplex data communication over 26 AWG and larger
twisted–pair cable up to two kilometers in distance. Intended primarily for use in
digital subscriber voice/data telephone systems, these devices can also be
used in remote data acquisition and control systems. These devices utilize a
256 kilobaud modified differential phase shift keying burst modulation technique
for transmission to minimize RFI/ EMI and crosstalk. Simultaneous power
distribution and duplex data communication can be obtained using a single
twisted–pair wire.
These devices are designed for compatibility with existing, as well as
evolving, telephone switching hardware and software architectures.
The UDLT chip–set consists of the MC145422 Master UDLT for use at the
telephone switch linecard and the MC145426 Slave UDLT for use at the remote
digital telset and/or data terminal.
The devices employ CMOS technology in order to take advantage of their
reliable low–power operation and proven capability for complex analog/digital
LSI functions.
• Provides Full–Duplex Synchronous 64 kpbs Voice/Data Channel and Two
8 kbps Signaling Data Channels Over One 26 AWG Wire Pair Up to Two
Kilometers
• Compatible with Existing and Evolving Telephone Switch Architectures and
Call Signaling Schemes
• Automatic Detection Threshold Adjustment for Optimum Performance Over
Varying Signal Attenuations
• Protocol Independent
• Single 5 V Power Supply
• 22–Pin PDIP, 24–Pin SOG Packages
• Application Notes AN943, AN949, AN968, AN946, and AN948
MC145422 Master UDLT
• Pin Controlled Power–Down and Loopback Features
• Signaling and Control I/O Capable of Sharing Common Bus Wiring with
Other UDLTs
• Variable Data Clock — 64 kHz to 2.56 MHz
• Pin Controlled Insertion/Extraction of 8 kbps Channel into LSB of 64 kbps
Channel for Simultaneous Routing of Voice and Data Through PCM Voice
Path of Telephone Switch
MC145426 Slave UDLT
• Compatible with MC145500 Series PCM Codec–Filters
• Pin Controlled Loopback Feature
• Automatic Power–Up/Power–Down Feature
• On–Chip Data Clock Recovery and Generation
• Pin Controlled 500 Hz D3 or CCITT Format PCM Tone Generator for
Audible Feedback Applications
Order this document
by MC145422/D
MC145422
MC145426
22
1
P SUFFIX
PLASTIC DIP
CASE 708
24
1
DW SUFFIX
SOG PACKAGE
CASE 751E
ORDERING INFORMATION
MC145422P Plastic DIP
MC145426P Plastic DIP
MC145422DW SOG Package
MC145426DW SOG Package
REV 2
9/95
©MOMoTtoOroRla,OInLc.A1995
DataSheet4 U .com
MC145422•MC145426
1
1 page  
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ANALOG CHARACTERISTICS (VDD = 5 V, TA = 0 to 70°C)
Parameter
Min
Modulation Differential Amplitude (RL = 440 Ω)
Modulation Differential DC Offset
LO1 to LO2
4.5
0
Demodulator Input Amplitude (See Note)
0.050
Demodulator Input lmpedance
50
NOTE: The input level into the demodulator to reliably demodulate incoming bursts. Input referenced to Vref.
MC145422 SWITCHING CHARACTERISTICS (VDD = 5 V, TA = 25°C, CL = 50 pF)
Figure
Parameter
No. Symbol
Input Rise Time
Input Fall Time
Pulse Width
CCI Duty Cycle
Data Clock Frequency
Propagation Delay Time
All Digital Inputs
All Digital Inputs
TDC/RDC, RE1, MSI
TDC/RDC
MSI to SO1, SO2 VD (PD = VDD)
TDC to Tx
1
1
1
1
—
2
3
tr
tf
tw(H,L)
tw(H,L)
tDC
tPLH, tPHL
MSI to TDC/RDC Setup Time
TE1/RE1 to TDC/RDC Setup Time
Rx to TDC/RDC Setup Time
Rx to TDC/RDC Hold Time
SI1, SI2 to MSI Setup Time
SI1, SI2 to MSI Hold Time
4 tsu3
tsu4
4 tsu3
tsu4
5 tsu5
5 th1
6 tsu6
6 th2
Min
—
—
90
45
64
—
—
90
40
90
40
60
60
60
60
MC145426 SWITCHING CHARACTERISTICS (VDD = 5 V, TA = 25°C, CL = 50 pF)
Parameter
Figure
No.
Symbol
Input Rise Time
All Digital Inputs
1
tr
Input Fall Time
Clock Output Pulse Width
All Digital Inputs
CLK
1
1
tf
tw(H,L)
Crystal Frequency
Propagation Delay Times
TE1 Rising to CLK (TE = VDD)
TE1 Rising to CLK (TE = VSS)
CLK to TE1 Falling
CLK to RE1 Rising
RE1 Falling to CLK (TE = VDD)
RE1 Falling to CLK (TE = VSS)
CLK to Tx
TE1 to SO1, SO2
—
7
7
7
8
8
8
9
9
fX1
tp1
tp1
tp2
tp3
tp4
tp4
tp5
tp6
Rx to CLK Setup Time
Rx to CLK Hold Time
SI1, SI2 to TE1 Setup Time
5 tsu5
5 th1
6 tsu6
SI1, SI2 to TE1 Hold Time
6 th2
Min
—
—
3.8
4.086
– 50
438
—
—
– 50
438
—
—
60
60
60
60
Max Unit
6.0 V p–p
300 mV
2.5 V peak
150 kΩ
Max
4
4
—
55
2560
90
90
—
—
—
—
—
—
—
—
Unit
µs
µs
ns
%
kHz
ns
ns
ns
ns
ns
ns
ns
Max Unit
4 µs
4 µs
4.0 µs
4.1 MHz
50 ns
538
40
40
50
538
90
90
— ns
— ns
— ns
— ns
MOTOROLA
DataSheet4 U .com
MC145422•MC145426
5
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Tx
Transmit Data Output
This is a standard B–series CMOS output. Voice data is
output on this pin on the rising edges of CLK while TE1 is
high and is high impedance when TE1 is low.
X1
Crystal Input
A 4.096 MHz crystal is tied between this pin and X2. A
10 MΩ resistor across X1 and X2 and 25 pF capacitors from
X1 and X2 to VSS are required for stability and to ensure
startup. X1 may be driven by an external CMOS clock signal
if X2 is left open.
X2
Crystal Output
This pin is capable of driving one external CMOS input and
15 pF of additional capacitance (see X1 pin description).
CLK
Clock Output
This is a standard B–series CMOS output which provides
the data clock for the telset codec–filter. It is generated by di-
viding the oscillator down to 128 kHz and starts upon the
completion of demodulation of an incoming burst from the
master. At this time, CLK begins and TE1 goes high. CLK will
remain active for 16 periods, at the end of which it will remain
low until another transmission from the master is demodu-
lated. In this manner, sync from the master is established in
the slave and any clock slip between the master and the
slave is absorbed each frame. CLK is generated in response
to an incoming burst from the master, however, if TE is
brought high, then CLK and TE1/RE1 are generated from the
internal oscillator until TE is brought low or an incoming burst
from the master is received. CLK is disabled when LB is held
low.
Rx
Receive Data Input
Voice data from the telset codec–filter is input on this pin
on the first eight falling edges of CLK after RE1 goes high.
Mu/A
Tone Digital Format Input
This pin determines if the PCM code of the 500 Hz square
wave tone, when TE is high, is Mu–Law (Mu/A = 1) or A–Law
(Mu/A = 0) format.
RE1
Receive Data Enable 1 Output
This is a standard B–series CMOS output which is the
inverse of TE1 (see TE1 pin description).
LO1, LO2
Line Driver Outputs
These outputs drive the twisted pair line with 256 kHz
modified DPSK bursts each frame and are push–pull. These
pins are driven to Vref when the device is not modulating.
BACKGROUND
The MC145422 master and MC145426 slave UDLT trans-
ceiver ICs main application is to bidirectionally transmit the
digital signals present at a codec–filter digital–PABX back-
plane interface over normal telephone wire pairs. This allows
the remoting of the codec–filter in a digital telephone set and
enables each set to have a high speed data access to the
PABX switching facility. In effect, the UDLT allows each
PABX subscriber direct access to the inherent 64 kbps data
routing capabilities of the PABX.
The UDLT provides a means for transmitting and receiving
64 kbits of voice data and 16 kbps of signaling data in two–
wire format over normal telephone pairs. The UDLT is a two–
chip set consisting of a master and a slave. The master
UDLT replaces the codec–filter and SLIC on the PABX line
card, and transmits and receives data over the wire pair to
the teleset. The UDLT appears to the linecard and backplane
as if it were a PCM Codec–Filter and has almost the same
digital interface features as the MC145500 series codec–fil-
ters. The slave UDLT is located in the telset and interfaces
the codec–filter to the wire pair. By hooking two UDLTs back–
to–back, a repeater can also be formed. The master and
slave UDLTs operate in a frame synchronous manner, sync
being established at the slave by the timing of the master’s
transmission. The master’s sync is derived from the PABX
frame sync.
The UDLT operates using one twisted pair. Eight bits of
voice data and two bits of signaling data are transmitted and
received each frame in a half–duplex manner (i.e., the slave
waits until the transmission from the master is completely re-
ceived before transmitting back to the master). Transmission
occurs at 256 kHz bit rate using a modified form of DPSK.
This “ping– pong” mode will allow transmission of data at dis-
tances up to two kilometers before turnaround delay be-
comes a problem. The UDLT is so defined as to allow this
data to be handled by the linecard, backplane, and PABX as
if it were just another voice conversation. This allows existing
PABX hardware and software to be unchanged and yet pro-
vides switched 64 kbps voice or data communications
throughout its service area by simply replacing a subscrib-
er’s linecard and teleset. A feature in the master allows one
of the two signaling bits to be inserted and extracted from the
backplane PCM word to allow simultaneous voice and data
transmission through the PABX. Both UDLTs have a loop-
back feature by which the device can be tested in the user
system.
The slave UDLT has the additional feature of providing a
500 Hz Mu–Law or A–Law coded square wave to the codec–
filter when the TE pin is brought high. This can be used to
provide audio feedback in the telset during keyboard depres-
sions.
CIRCUIT DESCRIPTION
GENERAL
The UDLT consists of a modulator, demodulator, two inter-
mediate data buffers, sequencing and control logic, and
transmit and receive data registers. The data registers
interface to the linecard or codec–filter digital interface sig-
nals, the modulator and demodulator interface the twisted
pair transmission medium, while the intermediate data regis-
ters buffer data between these two sections. The UDLT is
MOTOROLA
DataSheet4 U .com
MC145422•MC145426
11
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| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet MC145422.PDF ] | |
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