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PDF LP38859 Data sheet ( Hoja de datos )

Número de pieza LP38859
Descripción 3A Fast-Response High-Accuracy LDO Linear Regulator with Soft-Start
Fabricantes National Semiconductor 
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No Preview Available ! LP38859 Hoja de datos, Descripción, Manual

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June 2006
LP38859
3A Fast-Response High-Accuracy LDO Linear Regulator
with Soft-Start
General Description
Features
The LP38859 is a high current, fast response regulator n Standard VOUT values of 0.8V and 1.2V
which can maintain output voltage regulation with extremely n Stable with 10µF Ceramic capacitors
low input to output voltage drop. Fabricated on a CMOS
process, the device operates from two input voltages: VBIAS
provides voltage to drive the gate of the N-MOS power
transistor, while VIN is the input voltage which supplies
power to the load. The use of an external bias rail allows the
part to operate from ultra low VIN voltages. Unlike bipolar
regulators, the CMOS architecture consumes extremely low
quiescent current at any output load current. The use of an
N-MOS power transistor results in wide bandwidth, yet mini-
mum external capacitance is required to maintain loop sta-
bility.
The fast transient response of this device makes it suitable
n Dropout voltage of 240 mV (typical) at 3A load current
n Precision Output Voltage across all line and load
conditions:
±1.0% VOUT for TJ = 25˚C
±2.0% VOUT for 0˚C TJ +125˚C
±3.0% VOUT for -40˚C TJ +125˚C
n Over-Temperature and Over-Current protection
n Available in 5 lead TO-220 and TO-263 packages
n Custom VOUT values between 0.8V and 1.2V are
available
n −40˚C to +125˚C Operating Temperature Range
for use in powering DSP, Microcontroller Core voltages and
Switch Mode Power Supply post regulators. The LP38859 is
Applications
available in TO-220 and TO-263 5-Lead packages.
n ASIC Power Supplies In:
Dropout Voltage: 240 mV (typical) at 3A load current.
- Desktops, Notebooks, and Graphics Cards, Servers
Low Ground Pin Current: 14 mA (typical) at 3A load cur-
- Gaming Set Top Boxes, Printers and Copiers
rent.
n Server Core and I/O Supplies
Soft-Start: Programmable Soft-Start time.
Precision Output Voltage: ±1.0% for TJ =
25˚C
andD±a2t.a0S%heennt4DSUMS.cPPoSamnPdoFstP-RGeAguPloawtoerr
Supplies
for 0˚C TJ +125˚C, across all line and load conditions
Typical Application Circuit
DataShee
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© 2006 National Semiconductor Corporation
DS201312
20131201
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LP38859 pdf
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Typical Performance Characteristics Unless otherwise specified: TJ = 25˚C, VIN = VOUT(NOM) + 1V,
VBIAS = 3.0V, IOUT = 10 mA, CIN = COUT = 10 µF Ceramic, CBIAS = 1 µF Ceramic, CSS = open.
VBIAS Ground Pin Current (IGND(BIAS)) vs VBIAS
VBIAS Ground Pin Current (IGND(BIAS)) vs Temperature
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VIN Ground Pin Current vs Temperature
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Load Regulation vs Temperature
et4U.com
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Dropout Voltage (VDO) vs Temperature
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Output Current Limit (ISC) vs Temperature
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5
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LP38859 arduino
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Application Information (Continued)
et4U.com
Since the VOUT rise will be exponential, not linear, the in-rush
current will peak during the first time constant (τ), and VOUT
will require four additional time constants (4τ) to reach the
final value (5τ) .
After achieving normal operation, should VBIAS fall below the
ULVO threshold the device output will be disabled and the
Soft-Start capacitor (CSS) discharge circuit will become ac-
tive. The CSS discharge circuit will remain active until VBIAS
falls to 500 mV (typical). When VBIAS falls below 500 mV
(typical), the CSS discharge circuit will cease to function due
to a lack of sufficient biasing to the control circuitry.
Since VREF appears on the SS pin, any leakage through CSS
will cause VREF to fall, and thus affect VOUT. A leakage of 50
nA (about 10 M) through CSS will cause VOUT to be ap-
proximately 0.1% lower than nominal, while a leakage of 500
nA (about 1 M) will cause VOUT to be approximately 1%
lower than nominal. Typical ceramic capacitors will have a
factor of 10X difference in leakage between 25˚C and 85˚C,
so the maximum ambient temperature must be included in
the capacitor selection process.
Typical CSS values will be in the range of 1 nF to 100 nF,
providing typical Soft-Start times in the range of 70 µs to 7
ms (5τ). Values less than 1 nF can be used, but the Soft-
Start effect will be minimal. Values larger than 100 nF will
provide soft-start, but may not be fully discharged if VBIAS
falls from the UVLVO threshold to less than 500 mV in less
than 100 µs.
Figure 1 shows the relationship between the COUT value and
a typical CSS value.
vice. Under all possible conditions, the junction temperature
must be within the range specified under operating condi-
tions.
The total power dissipation of the device is the sum of three
different points of dissipation in the device.
The first part is the power that is dissipated in the NMOS
pass element, and can be determined with the formula:
PD(PASS) = (VIN - VOUT) x IOUT
(2)
The second part is the power that is dissipated in the bias
and control circuitry, and can be determined with the for-
mula:
PD(BIAS) = VBIAS x IGND(BIAS)
(3)
where IGND(BIAS) is the portion of the operating ground cur-
rent of the device that is related to VBIAS.
The third part is the power that is dissipated in portions of the
output stage circuitry, and can be determined with the for-
mula:
PD(IN) = VIN x IGND(IN)
(4)
where IGND(IN) is the portion of the operating ground current
of the device that is related to VIN.
The total power dissipation is then:
PD = PD(PASS) + PD(BIAS) + PD(IN)
(5)
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The maximum allowable junction temperature rise (TJ) de-
pends on the maximum anticipated ambient temperature
(TA) for the application, and the maximum allowable operat-
ing junction temperature (TJ(MAX)) .
(6)
The maximum allowable value for junction to ambient Ther-
mal Resistance, θJA, can be calculated using the formula:
DataShee
(7)
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FIGURE 1. Typical CSS vs COUT Values
The CSS capacitor must be connected to a clean ground
path back to the device ground pin. No components, other
than CSS, should be connected to the SS pin, as there could
be adverse effects to VOUT.
If the Soft-Start function is not needed the SS pin should be
left open, although some minimal capacitance value is al-
ways recommended.
POWER DISSIPATION AND HEAT-SINKING
Additional copper area for heat-sinking may be required
depending on the maximum device dissipation (PD) and the
maximum anticipated ambient temperature (TA) for the de-
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Heat-Sinking The TO-220 Package
The TO220-5 package has a θJA rating of 60˚C/W and a θJC
rating of 3˚C/W. These ratings are for the package only, no
additional heat-sinking, and with no airflow. If the needed
θJA, as calculated above, is greater than or equal to 60˚C/W
then no additional heat-sinking is required since the package
can safely dissipate the heat and not exceed the operating
TJ(MAX). If the needed θJA is less than 60˚C/W then addi-
tional heat-sinking is needed.
The thermal resistance of a TO-220 package can be reduced
by attaching it to a heat sink or a copper plane on a PC
board. If a copper plane is to be used, the values of θJA will
be same as shown in next section for TO-263 package.
The heat-sink to be used in the application should have a
heat-sink to ambient thermal resistance, θHA:
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