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T71L6816A Schematic ( PDF Datasheet ) - Taiwan Memory Technology

Teilenummer T71L6816A
Beschreibung Sixteen-port 10/100 Switch
Hersteller Taiwan Memory Technology
Logo Taiwan Memory Technology Logo 




Gesamt 22 Seiten
T71L6816A Datasheet, Funktion
www.DataSheet4U.com
tm TE
CH
Preliminary T71L6816A
Sixteen-port 10/100 Switch
________________________________________________________
The T71L6816A is a sixteen-port 10/100Mbps dual speed ethernet switch integrated with
a built-in 2K entries of address table and supports a 4Mb external SSRAM. T71L6816A is
also a high performance Fast-Ethernet switch with fully compliance with the IEEE802.3,
802.3u and 802.3x specifications. The T71L6816A can be implemented with external PHY chips
and 4Mb pipe-line SSRAM. By default, it is targeted for applications to the stand -alone
switch for low-cost SOHO and small enterprise market.
Features
l Support sixteen 10/100 Ethernet ports with RMII interface.
l External memory needed for 4Mb pipe-line SSRAM.
l Incorporating with private output buffering scheme to prevent HOL (head of line) blocking.
l Each port support priority-based queues with 4 levels and 802.1p QoS.
l Wire-speed store-and-forward switching with low latency.
l Automatic address learning with filtering of local frames or illegal frames.
l Embedded 2K entries of address look-up table.
l Support full/half duplex operations. DataSheet4U.com
l Support auto-negotiation via MDIO to detect speed and duplex status.
l Serial EEPROM interface for auto-configuration for features.
l Support IEEE802.3x flow control for full-duplex operation.
l Support Back-Pressure flow control for half-duplex operation.
l Support port-trunking mode to aggregate the bandwidth to provide the functions of load-sharing and
link backup.
l Support broadcast storm control scheme.
l Maximum 3 port-based VLAN groups can be defined by user.
l Support port-based port monitoring/snooping defined by user.
l Only one 50Mhz oscillator needed.
l 208-pin BGA, 3.3V with .18 µm CMOS technology.
DataShee
DataSheet4U.coTmaiwan Memory Technology, Copy-Right reserved.
Change to products or specifications without notice.
P. 1
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Publication Date:Jun. 2001
Revision:0.A






T71L6816A Datasheet, Funktion
www.DataSheet4U.com
tm TE
CH
Preliminary T71L6816A
3.4 Illegal Frames
The T71L6816A will check the errors of incoming frames and discard all illegal packets
if any non -recovered error found. The kinds of errors include FCS error, illegal packet
length, symbol error and dribble error. However, for preamble error, the T71L6816A will
try to identify the SFD even if the preamble error happened and the packet will be dropped
only if the T71L6808A can not well identify the incoming packet.
3.4.1 FCS Error
The T71L6816A will generate the 4 bytes of CRC checksum through every incoming packets
and compare the checksum with the FCS field to identify if the packet is corrupt or not.
If it is found that the CRC checksum is not matched with the FCS field, the T71L6816A
will discard this packet due to something wrong on data transmission.
et4U.com
3.4.2 Alignment Error
The T71L6816A will discard the packets with the frame length is of no n-integer in octet
unit. Exactly, the kind of such packet usually results in CRC checksum error and is called
as alignment error.
DataSheet4U.com
3.4.3 Dribble Error
Dribble error is that the packets contains some extra bit after four bytes of FCS. The
T71L6816A will drop those packets because those packets are usually similar to the FCS
error.
DataShee
3.4.4 Length of Frames
The T71L6816A can recognize the legal frame with length ranges from 64 bytes to 1522
bytes including four bytes of FCS. Any packet with length smaller than 64 bytes or larger
than 1522 bytes will be discarded.
3.5 Frame Forwarding
The first six bytes(DA) and the second six bytes(SA) of every incoming packet received
by T71L6816A will be retrieved and passed to Address Resolution Logic unit(ARL). The ARL
will use the SA to update the address table and use the DA to determine which destination
port the packet should be forwarded to by address table lookup.
DataSheet4U.coTmaiwan Memory Technology, Copy-Right reserved.
Change to products or specifications without notice.
P. 6
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Publication Date:Jun. 2001
Revision:0.A

6 Page









T71L6816A pdf, datenblatt
www.DataSheet4U.com
tm TE
CH
Preliminary T71L6816A
increasing from 01000b to 01111b after power on reset. The polling process will be
performing continuously to refresh the link status and the link partner’s abilities
such as speed, duplex and flow control until power off.
The following table shows the format of MDIO management frames:
Operation Preamble
Read
1……1
Write
1……1
ST
01
01
OP PHYaddr REGaddr
10 AAAAA RRRRR
01 AAAAA RRRRR
TA
Z0
10
DATA
DDDDDDDDDDDDDDDD
DDDDDDDDDDDDDDDD
3.17 Interface of 24LC02
3.17.1 Block Diagram
IDLE
Z
Z
et4U.com
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DataShee
The 24LC02 is an EEPROM chip providing 2K bits storage space with 2-wire I2C interface.
After power on reset, the T71L6816A will use a sequential read command to load the
configuration settings defined by user in the 24LC02 and configure the features from
those settings for later normal operation. Once loading completed, the T71L6816A will
tri-state the two pins SDA and SCLK to be ready for on-line updating 24LC02 through the
parallel port.
As shown above, the user can run a simple program on WinNT/Win98 to configure the external
24LC02 through the parallel port which is popular in most personal/notebook computer.
The whole system can then be reset after the external 24LC02 been reconfigured to adapt
for different environments.
DataSheet4U.coTmaiwan Memory Technology, Copy-Right reserved.
Change to products or specifications without notice.
P. 12
Publication Date:Jun. 2001
Revision:0.A
DataSheet4 U .com

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