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Teilenummer | EK7603 |
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Beschreibung | 480 / 402 Output Analog Source Driver For av Application Cog | |
Hersteller | Eureka Microelectronics | |
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Gesamt 16 Seiten www.DataSheet4U.com
֮ٙټጠ DOC Title Κ
EK7603 Data Sheet
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0.2
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REV Date
2003/˄/27
2003/6/5
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Eff. Date
2003/3/20
2003/6/˄7
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Revise item / Content
New Issue
˄. OSEL = H or open Æ H
OSEL = L Æ L or open
2. When EDGSL = L Æ L or open
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CONFIDENTIAL
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EUREKA
EK7603
4. PIN FUNCTION DESCRIPTION
Table 1. Pin description
Signal Name
Qa1 to Qa160
Qb1 to Qb160
Qc1 to Qc160
VA
VB
VC
L/R
Pin Type
Output
Input
Input
STH1
STH2
Bi-direction
Bi-direction
CPH1
CPH2
CPH3
Input
Function
Liquid-crystal application voltages
Each QaX, QbX or QcX correspond to one of the analog
sample input signal VA, VB or VC.
Video input signal
Analog video input signal that is sampled internally and
applied to the panel.
Controls the display data shift direction
L/R = H : STH1 input, Qa1→Qc160, STH2 output.
L/R = L : STH2 input, Qc160 →Qa1, STH1 output.
Right shift start pulse
L/R = H : Becomes the start pulse input pin
L/R = L : Becomes the start pulse output pin
Left shift start pulse
L/R = H : Becomes the start pulse output pin
L/R = L : Becomes the start pulse input pin
Sampling clock input
Refers to the analog data-sampling clock. The sampling starts
at the first rising edge of CPH1 when STH1 (L/R = H) is
activated. The sampling can be simultaneous or sequential.
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OE
OSEL
EDGSL
MODE
June 2003
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Input
Input
(Pull-down)
Input
(Pull-down)
Input
(Pull-down)
WheDn aintaSsihmeueltt4aUne.cooums mode (MODE = H), the sampling is
made during CPH1 period for all output, but CPH2 and CPH3
must be fixed to VDD or VSS.
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When in sequential mode (MODE = L, L/R = H), the sampling
is made according the table below:
CPH1 control the sampling for Qa1→Qa160
CPH2 control the sampling for Qb1→Qb160
CPH3 control the sampling for Qc1→ Qc160
When in sequential mode (MODE = L, L/R = L), the sampling
is made according the table below:
CPH1 control the sampling for Qc160→Qc 1
CPH2 control the sampling for Qb160→Qb1
CPH3 control the sampling for Qa160→Qa1
Load line
The sampled voltages are connecting to the panel at the
rising/falling edge (EDGSL) of OE. The outputs of SHA(B) that
was in sample mode are applied to the panel, whereas the
SHB(A) becomes ready to sample new values.
Number of output selection
CONFIDENTIALOSEL = H : 402 output mode
OSEL = L or open : 480 outputs mode
Output pins Qx68→ Qx93 are invalid in 402-output mode.
Output enable signal edge select.
When EDGSL = H, OE will be active at falling edge.
When EDGSL = L or open, OE will be active at rising edge.
Sampling mode selection
MODE = H: Simultaneous sampling
MODE = L or open: Sequentially sampling
- 5 - Preliminary Rev. 0.2
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6. ABSOLUTE MAXIMUM RATINGS
6.1 Absolute maximum ratings
Table 3. Absolute maximum ratings (VSS = AV SS = 0 V)
EK7603
Parameter
Logic Part Supply Voltage
Analog Part Supply Voltage
Logic Part Input Voltage
Video Input Voltage
Logic Part Output Voltage
Driver Part Output Voltage
Storage Temperature
Symbol
VDD
AVDD
VI 1
VI 2
VO1
VO2
TSTG
Rating
-0.5 to +7.0V
-0.5 to +7.0V
-0.5 to VDD + 0.5
-0.5 to AVDD + 0.5
-0.5 to VDD + 0.5
-0.5 to AVDD + 0.5
-55 to +125
Unit
V
V
V
V
V
V
°C
Caution: If the absolute maximum rating of even one of the above parameters is exceeded even
momentarily, the quality of the product may be degraded. Absolute maximum rating,
therefore, specify the values exceeding which the product may be physically damaged. Be
sure to use the product within thDeartaanSgheeeotf4tUh.ecoambsolute maximum rating.
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6.2 Recommended operating range
Table 4. Recommended operating range (VSS = AVSS = 0 V)
Parameter
Logic Part Supply Voltage
Analog Part Supply Voltage
Video Input Voltage
Symbol Conditions
VDD
AVDD
VVIDEO
MIN
2.7
4.5
AVSS + 0.2
Operating Ambient Temperature
Maximum Clock Frequency
OE period
TA
FCPH
TOE
-30
June 2003
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- 11 -
TYP MAX Unit
5.25
V
5.5 V
AVDD - 0.2 V
75 °C
10 MHz
64 200 µs
CONFIDENTIALPreliminary Rev. 0.2
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12 Page | ||
Seiten | Gesamt 16 Seiten | |
PDF Download | [ EK7603 Schematic.PDF ] |
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