PDF AS4LC2M8S0 Data sheet ( Hoja de datos )

Número de pieza	AS4LC2M8S0
Descripción	(AS4LCxMxxSx) 3.3V 2M X 8/1M X 16 CMOS synchronous DRAM
Fabricantes	Alliance Semiconductor
Logotipo
Hay una vista previa y un enlace de descarga de AS4LC2M8S0 (archivo pdf) en la parte inferior de esta página. Total 29 Páginas
No Preview Available ! www.DataSheet4U.com May 2001 AS4LC2M8S1 Preliminary AS4LC2M8S0 ® AS4LC1M16S1 3.3V 2M × 8/1M × 16 CMOS synchronous DRAM AS4LC1M16S0 Features • Organization - 1,048,576 words × 8 bits × 2 banks (2M × 8) 11 row, 9 column address - 524,288 words × 16 bits × 2 banks (1M × 16) 11 row, 8 column address • All signals referenced to positive edge of clock, fully synchronous • Dual internal banks controlled by A11 (bank select) • High speed - 143/125/100 MHz - 7/8/10 ns clock access time • Low power consumption - Active: 576 mW max - Standby: 7.2 mW max, CMOS I/O • 2048 refresh cycles, 32 ms refresh interval • 4096 refresh cycles, 64 ms refresh interval • Auto refresh and self refresh • PC100 functionality • Automatic and direct precharge including concurrent autoprecharge • Burst read, write/Single write • Random column address assertion in every cycle, pipelined operation • LVTTL compatible I/O • 3.3V power supply • JEDEC standard package, pinout and function - 400 mil, 44-pin TSOP 2 (2M × 8) - 400 mil, 50-pin TSOP 2 (1M × 16) • Read/write data masking • Programmable burst length (1/2/4/8/ full page) • Programmable burst sequence (sequential/interleaved) • Programmable CAS latency (1/2/3) Pin arrangement VCC DQ0 VSSQ DQ1 VCCQ DQ2 VSSQ DQ3 VCCQ NC NC WE CAS RAS CS A11 A10 A0 A1 A2 A3 VCC TSOP 2 1 44 2 43 3 42 4 41 5 40 6 39 7 38 8 37 9 36 10 35 11 34 12 33 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 21 24 22 23 LEGEND Configuration Refresh Count Row Address Bank Address Column Address Selection guide VSS DQ7 VSSQ DQ6 VCCQ DQ5 VSSQ DQ4 VCCQ NC NC DQM CLK CKE NC A9 A8 A7 A6 A5 A4 VSS VCC DQ0 DQ1 VSSQ DQ2 DQ3 VCCQ DQ4 DQ5 VSSQ DQ6 DQ7 VCCQ LDQM WE CAS RAS CS A11 A10 A0 A1 A2 A3 VCC 2M × 8 1M × 8 × 2 banks 2K/4K (A0 – A10) 2 (BA) 512 (A0 – A8) Pin designation TSOP 2 1 50 VSS Pin(s) 2 49 DQ15 3 48 DQ14 4 47 VSSQ DQM (2M × 8) UDQM/LDQM (1M × 16) 5 46 DQ13 6 45 DQ12 7 44 VCCQ 8 43 DQ11 A0 to A10 9 10 42 41 DDVaSQSQ1t0aSheet4U.com 11 40 DQ9 A11 12 39 DQ8 13 38 VCCQ DQ0 to DQ7 (2M × 8) 14 37 NC 15 36 UDQM DQ0 to DQ15 (1M × 16) 16 35 CLK 17 34 CKE RAS 18 33 NC 19 32 A9 CAS 20 31 A8 21 30 A7 WE 22 29 A6 23 28 A5 CS 24 27 A4 25 26 VSS VCC, VCCQ 1M × 16 512K × 16 × 2 banks 2K/4K VSS, VSSQ CLK (A0 – A10) 2 (BA) CKE 256 (A0 – A7) Symbol –7 –8 Description Output disable/write mask Address inputs CAR0A–07–(1×01D6a)taShee CA0 – 8 (×8) Bank address (BA) Input/output Row address strobe Column address strobe Write enable Chip select Power (3.3V ± 0.3V) Ground Clock input Clock enable –10 Unit Bus frequency (CL = 3) fMax 143 125 100 MHz Maximum clock access time (CL = 3) tAC 5.5 6 6 ns Minimum input setup time tS 2 2 2 ns Minimum input hold time tH 1.0 1.0 1.0 ns Row cycle time (CL = 3, BL = 1) tRC 70 80 80 ns Maximum operating current ([×16], RD or WR, CL = 3), BL = 2 ICC1 130 100 100 mA DataSheet4UM.caoximmum CMOS standby current, self refresh ICC6 1 1 1 mA 5/21/01; v.1.1 DataSheet4 U .com Alliance Semiconductor P. 1 of 29 Copyright ©Alliance Semiconductor. All rights reserved. 1 page www.DataSheet4U.com Mode register fields Address Function † RFU = 0 during MRS cycle. Write burst length A9 Length 0 Programmed burst length 1 Single burst AS4LC2M8S1 AS4LC1M16S1 ® Register programmed with MRS A11~A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 RFU† WBL TM CAS latency BT Burst length Burst type A3 Type 0 Sequential 1 Interleaved A8 0 0 1 1 heet4U.com A6 0 0 0 0 1 Test mode A7 Type 0 Mode register set 1 Reserved 0 Reserved 1 Reserved CAS latency A5 A4 Latency 0 0 Reserved 01 1 10 2 11 3 X X Reserved Burst sequence (burst length = 4) Initial address A1 A0 0 00 0 11 1 02 1 13 Burst sequence (burst length = 8) Initial address A2 A1 A0 0 0 00 0 0 11 0 1 02 0 1 13 1 0 04 1 0 15 1 1 06 1 1 17 DataSheet4U.com 1 2 3 4 5 6 7 0 A2 D a t a S h e e t 4 U0. c o m 0 0 0 1 1 1 1 Sequential 12 23 30 01 3 0 1 2 Sequential 234567 345670 456701 567012 670123 701234 012345 123456 Burst length A1 A0 BT = 0 BT = 1 0 0 11 0 1 22 1 0 44 1 1 88 0 0 Reserved Reserved 0 1 Reserved Reserved 1 0 Reserved Reserved 1 1 Full page Reserved Interleave 0123 1032 2301 3210 Interleave 01234567 10325476 23016745 32107654 45670123 54761032 67452301 76543210 DataSh 5/21/01; v.1.1 D a t a S h e4eUt . c o m Alliance Semiconductor P. 5 of 29 5 Page www.DataSheet4U.com et4U.com AS4LC2M8S1 AS4LC1M16S1 ® Command Pin settings Description Use the Burst Write command to write data into the SDRAM on Burst write CS = CAS = WE = A10 = low; RAS = high; A0~A9 = column address; (A9 = don’t care for 2M × 8; A8, A9 = don’t care for 1M × 16) consecutive clock cycles to adjacent column addresses. The burst length and addressing mode is determined by the mode register opcode. Input the initial write address in the same clock cycle as the Burst Write command. Burst terminate behavior for write is the same as that for read. Terminate the burst with a burst stop command, precharge command to the same bank or another burst read/write. DQM can also be used to mask the input data. UDQM/LDQM (×16) DQM (×8) operation Use DQM to mask input and output data. It disables the output buffers in a read operation and masks input data in a write operation. The output data is invalid 2 clocks after DQM assertion (2 clock latency). Input data is masked on the same clock as DQM assertion (0 clock latency). Burst stop CS = WE = low; RAS = CAS = Use burst stop to terminate burst operation. This command may be high used to terminate all legal burst lengths. The Bank Precharge command precharges the bank specified by A11. CS = A10 = RAS = WE = low; The precharged bank is switched from active to idle state and is ready Bank precharge Precharge all CAS = high; A11 = bank to be activated again. Assert the precharge command after tRAS(min) of select; A0~A9 = don’t care the bank activate command in the specified bank. The precharge operation requires a time of tRP(min) to complete. CS = A10 R=AhSi=gdhoW;nA’Et1c=1ar,leoAw0~; CAA9S=D=atTBaohStehhPebreeacnt4hkaUsrag.creeoAmswll ictochmemd atondthpereidchlearsgtaetse both banks simultaneously. on precharge completion. During auto precharge, the SDRAM adjusts internal timing to satisfy Auto precharge Write: CS = CAS = WE = low ; Read: CS = CAS = low; A10 = high; A11 = bank select; A0~A9 = column address; (A9 = don’t care for 2M × 8; A8, A9 = don’t care for 1M × 16) tRAS(min) and tRP for the programmed CAS latency and burst length. Couple the auto precharge with a burst read/write operation by asserting A10 to a high state at the same time the burst read/write commands are issued. At auto precharge completion, the specified bank is switched from active to idle state. Note that no new commands (RD/WR/DEAC) can be issued to the same bank until the specified bank achieves the idle state. Auto precharge does not work with full- page burst. When CKE is low, the internal clock is frozen or suspended from the next clock cycle and the state of the output and burst address are Clock suspend/power down mode entry CKE = low frozen. If both banks are idle and CKE goes low, the SDRAM enters power down mode at the next clock cycle. When in power down mode, no input commands are acknowledged as long as CKE remains low. To exit power down mode, raise CKE high before the rising edge of CLK. Clock suspend/power down mode exit CKE = high Resume internal clock operation by asserting CKE high before the rising edge of CLK. Subsequent commands can be issued one clock cycle after the end of the Exit command. DataShee DataSheet4U.com 5/21/01; v.1.1 DataSheet4 U .com Alliance Semiconductor P. 11 of 29 11 Page

Páginas	Total 29 Páginas
PDF Descargar	[ Datasheet AS4LC2M8S0.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
AS4LC2M8S0	(AS4LCxMxxSx) 3.3V 2M X 8/1M X 16 CMOS synchronous DRAM	Alliance Semiconductor
AS4LC2M8S1	(AS4LCxMxxSx) 3.3V 2M X 8/1M X 16 CMOS synchronous DRAM	Alliance Semiconductor

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar