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DJLXT971ALCA4S Schematic ( PDF Datasheet ) - Intel

Teilenummer DJLXT971ALCA4S
Beschreibung Dual Speed Fast Ethernet PHY Transceiver
Hersteller Intel
Logo Intel Logo 



Gesamt 30 Seiten
		
DJLXT971ALCA4S Datasheet, Funktion
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Intel® LXT971A
3.3V Dual-Speed Fast Ethernet PHY Transceiver
Datasheet
The LXT971A is an IEEE compliant Fast Ethernet PHY Transceiver that directly supports both
100BASE-TX and 10BASE-T applications. It provides a Media Independent Interface (MII) for
easy attachment to 10/100 Media Access Controllers (MACs). The LXT971A also provides a
Low Voltage PECL (LVPECL) interface for use with 100BASE-FX fiber networks.
This document also supports the LXT971 device.
The LXT971A supports full-duplex operation at 10 Mbps and 100 Mbps. Its operating condition
can be set using auto-negotiation, parallel detection, or manual control.
The LXT971A is fabricated with an advanced CMOS process and requires only a single 3.3V
power supply.
Applications
Combination 10BASE-T/100BASE-TX or 10/100 PCMCIA Cards
100BASE-FX Network Interface Cards
(NICs)
Cable Modems and Set-Top Boxes
Product Features
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3.3V Operation.
Low power consumption (300 mW
typical).
Low-power “Sleep” mode.
10BASE-T and 100BASE-TX using a
single RJ-45 connection.
Supports auto-negotiation and parallel
detection.
MII interface with extended register
capability.
Robust baseline wander correction
performance.
100BASE-FX fiber-optic capable.
Standard CSMA/CD or full-duplex
operation.
Supports JTAG boundary scan.
Configurable via MDIO serial port or
hardware control pins.
Integrated, programmable LED drivers.
64-ball Plastic Ball Grid Array (PBGA).
— LXT971ABC - Commercial (0° to
70°C ambient).
— LXT971ABE - Extended (-40° to 85°C
ambient).
64-pin Low-profile Quad Flat Package
(LQFP).
— LXT971ALC - Commercial (0° to
70°C ambient).
— LXT971ALE - Extended (-40° to 85°C
ambient).
DataShee
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Order Number: 249414-002
August 2002






DJLXT971ALCA4S Datasheet, Funktion
www.DataSheet4U.com
LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver
et4U.com
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
LQFP Numeric Pin List .................................................................................................... 12
LXT971A MII Signal Descriptions .................................................................................. 14
LXT971A Network Interface Signal Descriptions ........................................................... 15
LXT971A Miscellaneous Signal Descriptions ................................................................. 16
LXT971A Power Supply Signal Descriptions.................................................................. 17
LXT971A JTAG Test Signal Descriptions ...................................................................... 17
LXT971A LED Signal Descriptions ................................................................................ 17
Hardware Configuration Settings ..................................................................................... 26
Carrier Sense, Loopback, and Collision Conditions......................................................... 32
4B/5B Coding ................................................................................................................... 36
BSR Mode of Operation ................................................................................................... 43
Supported JTAG Instructions ........................................................................................... 43
Device ID Register ........................................................................................................... 43
Magnetics Requirements .................................................................................................. 44
I/O Pin Comparison of NIC and Switch RJ-45 Setups..................................................... 44
Absolute Maximum Ratings ............................................................................................. 49
Operating Conditions........................................................................................................ 49
Digital I/O Characteristics 1 ............................................................................................. 50
Digital I/O Characteristics - MII Pins............................................................................... 50
I/O Characteristics - REFCLK/XI and XO Pins............................................................... 50
I/O Characteristics - LED/CFG Pins ................................................................................ 50
100BASE-TX Transceiver Characteristics....................................................................... 51
100BASE-FX Transceiver Characteristics ....................................................................... 51
10BASE-T TransceiverDCahtaarSahcteeerits4tUic.sc..o..m........................................................................ 51
10BASE-T Link Integrity Timing Characteristics ........................................................... 52
100BASE-TX Receive Timing Parameters - 4B Mode.................................................... 53
100BASE-TX Transmit Timing Parameters - 4B Mode .................................................. 54
100BASE-FX Receive Timing Parameters ...................................................................... 55
100BASE-FX Transmit Timing Parameters..................................................................... 56
10BASE-T Receive Timing Parameters........................................................................... 57
10BASE-T Transmit Timing Parameters ......................................................................... 58
10BASE-T Jabber and Unjabber Timing Parameters....................................................... 59
10BASE-T SQE Timing Parameters ................................................................................ 59
Auto Negotiation and Fast Link Pulse Timing Parameters .............................................. 60
MDIO Timing Parameters ................................................................................................ 61
Power-Up Timing Parameters .......................................................................................... 62
RESET Pulse Width and Recovery Timing Parameters.................................................. 62
Register Set....................................................................................................................... 63
Register Bit Map............................................................................................................... 64
Control Register (Address 0) ............................................................................................ 66
MII Status Register #1 (Address 1) .................................................................................. 67
PHY Identification Register 1 (Address 2)....................................................................... 68
PHY Identification Register 2 (Address 3)....................................................................... 68
Auto Negotiation Advertisement Register (Address 4).................................................... 69
Auto Negotiation Link Partner Base Page Ability Register (Address 5) ......................... 70
Auto Negotiation Expansion (Address 6)......................................................................... 71
Auto Negotiation Next Page Transmit Register (Address 7) ........................................... 71
Auto Negotiation Link Partner Next Page Receive Register (Address 8)........................ 72
Configuration Register (Address 16, Hex 10) .................................................................. 73
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Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
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DJLXT971ALCA4S pdf, datenblatt
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
1.0 Pin Assignments
et4U.com
Figure 2. LXT971A 64-Ball PBGA Assignments
12345678
A MDINT CRS TXD3 TXD0 RX_ER VCCD RX_DV RXD0 A
B
REF
CLK/XI
COL
TXD2 TX_EN TX_ER
RX_
CLK
N/C RXD1 B
C XO
RESET GND
TXD1
TX_
CLK
GND
N/C
RXD2 C
D
Tx
SLEW0
Tx
SLEW1
MDDIS
GND
VCCIO
RXD3
N/C
MDIO D
E ADDR0 ADDR1 GND GND VCCIO
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F ADDR3 ADDR2 GND GND
TDI
LED/
CFG1
TMS
MDC
LED/
CFG2
PWR
DWN
E
LED/
CFG3
F
G ADDR4 SD/TP VCCA VCCA TDO TCK GND GND G
H RBIAS TPFOP TPFON TPFIP TPFIN TRST SLEEP PAUSE H
12345678
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Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002

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