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Número de pieza | LQ035Q7DH06 | |
Descripción | Advanced TFT-LCD Module 240 x RGB x 320 pixels | |
Fabricantes | Sharp Microelectronics | |
Logotipo | ||
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PRODUCT SPECIFICATIONS
Liquid Crystal Displays Group
LQ035Q7DH06
Advanced TFT-LCD Module
DataSheet4U.com
240 × RGB × 320 pixels
DataShee
(Spec. No.: LCP-05020B)
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Spec. Issue Date: July 15, 2005
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(1) Application
This specification applies to LQ035Q7DH06
LCP-05020-2
(2) Overview
This module is a color active matrix LCD module incorporating amorphous silicon TFT (Thin Film
Transistor), named AD-TFT (Advanced TFT). It is practicable in both transmissive-type and reflection-
type modes. It is composed of a color TFT-LCD panel, driver ICs, an FPC, a back light, a touch panel and
a back sealed casing. It isn’t composed control circuit. Graphics and texts can be displayed on a
240×3×320 dots panel with 262,144 colors by supplying.
Optimum view angle is 6 o’clock. An inverted display mode is selective in the vertical or the horizontal
direction.
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(3) Mechanical specifications
Table 1
Parameter
Specifications
Screen size (Diagonal)
8.9 [3.52"] Diagonal
Display active area
53.64(H) × 71.52(V)
Pixel format
240(H) × 320(V)
(1 pixel = R+G+B dots)
Pixel pitch
0.2235(H) × 0.2235(V)
Pixel configuration
R,G,B vertical stripe
Unit outline dimension
65.0(W) × 86.2(H) × 4.0(D)
Mass
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B Surface hardness
【Note 3-1】
2H
Excluding protrusion, Including FPC cover portion
For detailed measurements and tolerances, please refer to Fig. 1.
Units
cm
mm
pixels
Remarks
mm
mm 【Note3-1】
g TYP.
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(4) Pixel configuration
RGB
(1,1)
(240,1)
Display area
FPC
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(1,320)
(240,320)
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5 Page www.DataSheet4U.com
LCP-05020-8
7-2) Timing Characteristics of input signals
Table 7 AC Characteristics (1)
(VSHA=+5V, VSHD=+3.3V, Ta=25℃)
Parameter
Symbol Min. Typ.
Max.
Unit
Remark
Clock frequency of source driver
fCK 4.5 -
6.8 MHz
Rising time of clock
Tcr - - 20 ns
Falling time of clock
Tcf - - 20 ns DCLK
Pulse width (High level)
Tcwh 40 -
-
ns
Pulse width (Low level)
Tcwl
40 -
-
ns
Frequency of start pulse
fsp 16.5 -
28 kHz
Setup time of start pulse Tsusp 15 - - ns SPL,SPR
Source Hold time of start pulse
Thsp 10 -
driver Pulse width of start pulse
Twsp
-
-
Setup time of latch pulse Tsulp 20 -
-
1.5/fCK
-
ns
ns 【Note 7-7】
ns
Hold time of latch pulse
Thlp
20 -
-
ns LP
Pulse width of latch pulse Twlp
60 -
-
ns
Setup time of PS
Tsups 0 - - μs
Setup time of PS
Hold time of PS
Tsulps 1 - - μs PS
Thps
0-
-
μs
Hold time of PS
Thlps 30 - - ns
Set up time of data
Tsud
15 -
-
ns R0~R5,G0~G5
Hold time of data
Thd 10 - - ns ,B0~B5
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Clock frequency
Pulse width of clock(Low)
DfcalstaShee1t46U.5.com-
Twlcls 5 -
28
(1/fcls)-30
kHz
μs
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Pulse width of clock(High) Twhcls 30
-
-
μs
Rising time of clock
Trcls
--
100
ns CLS
Falling time of clock
Tfcls
--
100
ns
Gate Setup time of clock
Tsucls 3 - - μs
driver Hold time of clock
Thcls 0 - - μs
Frequency of start pulse
fsps 58 -
86
Hz
Setup time of start pulse
Tsusps 100 -
-
ns
Hold time of start pulse
Thsps 300 -
-
ns SPS
Rising time of start pulse
Trsps
--
100
ns
Falling time of start pulse Tfsps - - 100 ns
Vcom Setup time of Vcom
Tsuvcom 0
-
-
μs Vcom
Hold time of Vcom
Thvcom 1
-
-
μs
【Note 7-7】There must be only one up-edge of DCLK (includes Tsusp and Thsp time) in the period of
SPL=”Hi”.
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11 Page |
Páginas | Total 26 Páginas | |
PDF Descargar | [ Datasheet LQ035Q7DH06.PDF ] |
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