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UC1606 Schematic ( PDF Datasheet ) - Ultra Chip

Teilenummer UC1606
Beschreibung 65COM x 132SEG Matrix LCD Controller-Driver
Hersteller Ultra Chip
Logo Ultra Chip Logo 




Gesamt 46 Seiten
UC1606 Datasheet, Funktion
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HIGH-VOLTAGE MIXED-SIGNAL IC
65COM x 132SEG Matrix LCD Controller-Driver
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Product Specifications
Version 1.32
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September 24, 2003
ULTRACHIP
The Coolest LCD Driver. Ever!!
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UC1606 Datasheet, Funktion
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ULTRACHIP
High-Voltage Mixed-Signal IC
©1999-2003
PIN DESCRIPTION
Name Type
Pins
VDD
VDD2
VDD3
VSS
VSS2
PWR
GND
VB1+ VB1–
VB0+ VB0–
PWR
VLCD-IN
VLCD-OUT
PWR
Description
MAIN POWER SUPPLY
VDD2/VDD3 is the analog power supply and it should be connected to the
same power source. VDD is the digital power supply and it should be
connected to a voltage source that is no higher than VDD2/VDD3.
Minimize the trace resistance for VDD and VDD2/VDD3.
Ground. Connect VSS and VSS2 to the shared GND pin.
Minimize the trace resistance for VSS and VSS2.
LCD POWER SUPPLY
LCD Bias Voltages. These are the voltage sources to provide SEG
driving currents. These voltages are generated internally. Connect
capacitors of CBX value between VBX+ and VBX–.
The resistance of these four traces directly affects the SEG driving
strength of the resulting LCD module. Minimize the trace resistance is
critical in achieving high quality image.
Main LCD Power Supply. Connect these pins together.
A by-pass capacitor CL is optional. When CL is used, connect CL
between VLCD and VSS, and keep the trace resistance under 300 Ohm.
NOTE
In COG applications, use one maximumDawtaidSthhteraecte4Uto.ccoonmnect VDD/VDD2/VDD3 to the LCM pad to
minimize trace resistance. However, to avoid noise cross-coupling, insert a slit, 0.2~0.3mm long,
between VDD/VDD2/VDD3. Same treatment for VSS/VSS2.
Recommended capacitor values:
CB: 150 ~ 250x LCD load capacitance or 1.0uF (2V), whichever is higher.
CL: 5nF ~ 20nF (16V) is appropriate for most applications.
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UC1606 pdf, datenblatt
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ULTRACHIP
High-Voltage Mixed-Signal IC
©1999-2003
COMMAND DESCRIPTION
(1) Write data to display memory
Action
Write data
(2) Read data to display memory
Action
Read data
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
10
8bits data write to SRAM
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
11
8bits data from SRAM
Write/Read Data Byte (command 1,2 ) operation accesses display buffer RAM based on Page Address (PA)
register and Column Address (CA) register. To minimize bus interface cycles, PA and CA will be increased
or decreased automatically depending on the setting of Access Control (AC) registers. PA and CA can also
be programmed directly by issuing Set Page Address and Set Column Address commands.
If Wrap-Around (WA) is OFF (AC[0] = 0), CA will stop increasing after reaching the end of page (MC), and
system programmers need to set the values of PA and CA explicitly. If WA is ON (AC[0]=1), when CA
reaches end of page, CA will be reset to 0 and PA will be increased or decreased by 1, depending on the
setting of Page Increment Direction (PID, AC[2]). When PA reaches the boundary of RAM (i.e. PA = 0 or 31),
PA will be wrapped around to the other end of RAM and continue.
(3) Get Status
Action
Get Status
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
0Data1SheBeZt4UM.XcomDE RS 0 0 0 0
Status flag definitions:
BZ: Busy with internal process. When BZ=1 host interface can access if RS=0.
MX: Status of register LC[2], mirror X.
DE: Display enable flag. DE=1 when display enabled
RS: Reset in progress. If RS=1, host interface will be inaccessible.
(4) Set Column Address
Action
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
Set Column Address LSB CA[3:0]
0 0 0 0 0 0 CA3 CA2 CA1 CA0
Set Column Address MSB CA[7:4] 0 0 0 0 0 1 CA7 CA6 CA5 CA4
Set the SRAM column address before Write/Read memory from host interface.
CA possible value=0-131
(5) Set Gain
Action
C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
Set Gain GN[2:0]
0 0 0 0 1 0 0 GN2 GN1 GN0
Program Gain (GN[2:0]) . See section LCD VOLTAGE SETTING for more detail.
GN[2:0]
000 001 010 011 100 101 110 111
Gain 1.43 1.58 1.72 1.89 2.08 2.28 2.49 2.72
10
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