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PDF T8207 Data sheet ( Hoja de datos )
| Número de pieza | T8207 | |
| Descripción | ATM Interconnect | |
| Fabricantes | Agere Systems | |
| Logotipo |  |
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Advance Data Sheet
September 2001
CelXpres™ T8207
ATM Interconnect
1 Product Overview
1.1 Features
s Programmable priority for control/data cells trans-
mission onto cell bus
s Eight GPIO pins
s > OC-3 transport capability
s JTAG support
s UTOPIA level 1 and 2 (8-bit) cell-level handshake
s Optional monitoring of misrouted cells
interface (ATM or PHY layers)
s 32 multi-PHY (MPHY) operation
s Microprocessor interface, supporting both Motor-
ola® and Intel® modes (multiplexed and nonmulti-
plexed)
s Shared UTOPIA mode
s Control cell transmission and reception through
s Egress SDRAM buffer support to expand UTOPIA
microprocessor port
output priority queues for 32K to 512K cells:
— 64 queues configurable up to four queues per
s Single 3.3 V power supply
PHY with programmable sizes
s 3.3 V TTL I/O (5 V tolerant)
— Programmable number of UTOPIA output
queues with four levels of priority
s 272-pin PBGA package
s Support of ATM traffic management via partial
s Industrial temperature range (–40 °C to +85 °C)
packet discard (PPD), forward explicit DcoantagSehsetioent4U.coms Hot insertion capability
DataShee
notification (FECN), and the cell loss priority (CLP)
bit
s Compatible with Transwitch CellBus®
s Programmable slew rate GTL+ I/O:
— 1.7 Gbits/s cell bus operation
— Programmable as bus arbiter
s Flexible per port cell counters
s Cell header translation and insertion with virtual
path identifier (VPI) and virtual channel identifier
(VCI) via external SRAM (up to 64K entries)
1.2 Applications
s Asymmetric digital subscriber line (ADSL) digital
subscriber line access multiplexer (DSLAMs)
s Access gateways
s Access multiplexers/concentrators
s Support of network node interface (NNI) and user
network interface (UNI) header types with optional
generic flow control (GFC) insertion
s Multiservice access equipment platforms
s Programmable operations and maintenance and
resource management (OAM/RM) cell routing
s Support of multicast and broadcast cells per PHY
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Advance Data Sheet
September 2001
CelXpres T8207
ATM Interconnect
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Table of Contents (continued)
Table
Page
Table 1. UTOPIA Pins ........................................................................................................................................... 13
Table 2. Cell Bus Pins ........................................................................................................................................... 14
Table 3. SDRAM Interface Pins ............................................................................................................................ 15
Table 4. Microprocessor Interface Pins ................................................................................................................. 16
Table 5. Translation SRAM Interface ..................................................................................................................... 17
Table 6. JTAG Pins ............................................................................................................................................... 17
Table 7. General-Purpose Pins ............................................................................................................................. 18
Table 8. Power Pins .............................................................................................................................................. 18
Table 9. Loop Filter Register Settings .................................................................................................................... 22
Table 10. Access Times ........................................................................................................................................ 25
Table 11. Active and Ignore Truth Table ............................................................................................................... 31
Table 12. VPI Value Truth Table ........................................................................................................................... 32
Table 13. OAM Routing Control Truth Table ......................................................................................................... 32
Table 14. F5 Translation Record Addresses Table—8-Byte Records ................................................................... 33
Table 15. F5 Translation Record Addresses Table—Extended Mode ................................................................... 40
Table 16. Port Numbering for MPHY Configurations ............................................................................................ 51
Table 17. Supported Memory Configurations ....................................................................................................... 64
Table 18. Queue Organization and Port Group Address/Priority Bits for 16 Ports with T8207_sel = 1 ................. 67
Table 19. Queue Organization and Port Group Address/Priority Bits for 32 Ports ................................................ 69
Table 20. Queue Organization and Port Group Address/Priority Bits for 16 Ports with T8207_sel = 0................... 71
Table 21. Instruction Register ............................................................................................................................... 75DataShee
Table 22. Boundary-Scan Register Descriptions .................................................................................................. 76
Table 23. Register Map ................................D...a..t.a..S..h..e..e..t.4..U....c..o..m................................................................................ 79
Table 24. Identification 0 (IDNT0) (00h) ................................................................................................................ 82
Table 25. Identification 1 (IDNT1) (01h) ................................................................................................................. 82
Table 26. Identification 2 (IDNT2) (02h) ................................................................................................................ 82
Table 27. Direct Configuration/Control Register (DCCR) (28h) ............................................................................. 83
Table 28. Interrupt Service Request (ISREQ) (29h) ............................................................................................. 84
Table 29. mclk PLL Configuration 0 (MPLLCF0) (2Ah) ......................................................................................... 84
Table 30. mclk PLL Configuration 1 (MPLLCF1) (2Bh) ......................................................................................... 85
Table 31. GTL+ Slew Rate Configuration (GTLSRCF) (2Eh) ................................................................................ 85
Table 32. GTL+ Control (GTLCNTRL) (2Fh)........................................................................................................... 85
Table 33. Extended Memory Address 1 (Little Endian) (EMA1_LE) (30h)............................................................. 86
Table 34. Extended Memory Address 2 (Little Endian) (EMA2_LE) (31h)............................................................. 86
Table 35. Extended Memory Address 3 (Little Endian) (EMA3_LE) (32h)............................................................. 86
Table 36. Extended Memory Address 4 (Little Endian) (EMA4_LE) (33h)............................................................. 86
Table 37. Extended Memory Access (Little Endian) (EMA_LE) (34h) ................................................................... 86
Table 38. Extended Memory Data Low (Little Endian) (EMDL_LE) (36h) ............................................................. 87
Table 39. Extended Memory Data High (Little Endian) (EMDH_LE) (37h) ............................................................ 87
Table 40. Extended Memory Address 4 (Big Endian) (EMA4_BE) (30h)............................................................... 88
Table 41. Extended Memory Address 3 (Big Endian) (EMA3_BE) (31h)............................................................... 88
Table 42. Extended Memory Address 2 (Big Endian) (EMA2_BE) (32h)............................................................... 88
Table 43. Extended Memory Address 1 (Big Endian) (EMA1_BE) (33h)............................................................... 88
Table 44. Extended Memory Access (Big Endian) (EMA_BE) (34h) ..................................................................... 89
Table 45. Extended Memory Data High (Big Endian) (EMDH_BE) (36h) .............................................................. 89
Table 46. Extended Memory Data Low (Big Endian) (EMDL_BE) (37h) ............................................................... 89
Table 47. GPIO Output Enable (GPIO_OE) (39h) ................................................................................................. 90
Table 48. GPIO Output Value (GPIO_OV) (3Bh) ................................................................................................... 90
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Advance Data Sheet
September 2001
CelXpres T8207
ATM Interconnect
1 Product Overview (continued)
1.4 Conventions
s All numbers in this document are decimals unless otherwise specified.
s Hexadecimal numbers can be identified by the ‘h’ suffix, e.g., A5h.
s Binary numbers are either in double quotes for multiple bits or in single quotes for individual bits, e.g., “1001” and
‘0.’
s A byte is 8 bits, a word is 16 bits, and a double word (dword) is 32 bits.
s A binary value of ‘1’ is high, and a binary value of ‘0’ is low.
s To clear is to change one or multiple bit values to ‘0.’
s To set is to change one or multiple bit values to ‘1.’
s All memory addresses are specified in hexadecimal.
s Addresses are converted from bytes to words or double words using the little-endian format, unless otherwise
specified.
s A signal name with a trailing asterisk is active-low, e.g., sd_we*.
s Bits y to x will be designated bits (y:x).
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