|
|
PDF MB81F161622C Data sheet ( Hoja de datos )
| Número de pieza | MB81F161622C | |
| Descripción | 2 x 512K x 16-Bit SDRAM | |
| Fabricantes | Fujitsu | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MB81F161622C (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-11056-1E
MEMORY
CMOS
2 × 512 K × 16 BIT
SYNCHRONOUS DYNAMIC RAM
MB81F161622C-60/-70/-80/-80L
CMOS 2-Bank × 524,288-Word × 16 Bit
Synchronous Dynamic Random Access Memory
s DESCRIPTION
The Fujitsu MB81F161622C is a CMOS Synchronous Dynamic Random Access Memory (SDRAM) containing
16,777,216 memory cells accessible in an 16-bit format. The MB81F161622C features a fully synchronous
operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which
enables high performance and simple user interface coexistence. The MB81F161622C SDRAM is designed to
reduce the complexity of using a standard dynamic RAM (DRAM) which requires many control signal timing
constraints, and may improve data bandwidth of memory as much as 5 times more than a conventional DRAM.
The MB81F161622C is ideally suited for laser printers, high resolution graphic adapters, accelerators and other
applications where an extremely large memory and bandwidth are required and where a simple interface is
needed.
s PRODUCT LINE & FEATURES
Parameter
CL - tRCD - tRP
Clock Frequency (CL = 3)
Burst Mode Cycle Time (CL = 3)
Access Time From Clock (CL = 3)
Operating Current
Power Down Mode Current (ICC2P)
Self Refresh Mode Current (ICC6)
-60
3 - 3 - 3 clk min.
167 MHz max.
6.0 ns min.
5.5 ns max.
150 mA max.
1 mA max.
1 mA max.
MB81F161622C
-70
-80/-80L
Reference Spec
(100MHz @CL=3)
3 - 3 - 3 clk min. 3 - 3 - 3 clk min. 3 - 3 - 3 clk min.
143 MHz max. 125 MHz max.
100 MHz max.
7.0 ns min.
8.0 ns min.
10 ns min.
6 ns max.
6 ns max.
6 ns max.
130 mA max.
110 mA max.
90 mA max.
1 mA max.
1 mA max.
1 mA max.
1 mA max. 1 mA / 400 µA max. 1 mA max.
• Single +3.3 V Supply: +0.3 V / −0.15 V tolerance (-60)
±0.3 V tolerance (-70/-80/-80L)
• LVTTL compatible I/O interface
• 4 K refresh cycles every 64 ms
• Dual banks operation
• Burst read/write operation and burst
read/single write operation capability
• Byte control by DQMU/DQML
• Programmable burst type, burst length,
and CAS latency
• Auto-and Self-refresh (every 15.6 µs)
• CKE power down mode
• Output Enable and Input Data Mask
• 167 MHz/143MHz/125 MHz clock frequency
DataSheet4 U .com
www.DataSheet4U.com
www.DataSheet4U.com
1 page  
www.DataSheet4U.com
MB81F161622C-60/-70/-80/-80L
s FUNCTIONAL TRUTHAL TABLE (Note *1)
COMMAND TRUTH TABLE Notes *2,*3, and *4
Function
CKE
Notes Symbol
n-1 n
Device Deselect
*5 DESL H X
No Operation
*5 NOP H X
Burst Stop
BST H X
Read
*6 READ H X
Read with Auto-precharge
*6 READA H X
Write
*6 WRIT H X
Write with Auto-precharge
*6 WRITA H X
Bank Active (RAS)
*7 ACTV H X
Precharge Single Bank
PRE H X
Precharge All Banks
PALL H X
Mode Register Set
*8,*9 MRS H X
CS
RAS CAS
WE
A11
(BA)
A10
(AP)
A9, A8
A7 to
A0
HXXXXX
L HHHX X
LHHL XX
L H L HV L
LHLHVH
LHL LVL
LHL LVH
L LHHVV
L LHLVL
L LHLXH
LLLLLL
X
X
X
X
X
X
X
V
X
X
V
X
X
X
V
V
V
V
V
X
X
V
Notes: *1.
*2.
*3.
*4.
*5.
*6.
*7.
*8.
*9.
V = Valid, L = Logic Low, H = Logic High, X = either L or H
All commands assume no CSUS command on previous rising edge of clock.
All commands are assumed to be valid state transitions.
All inputs are latched on the rising edge of clock.
NOP and DESL commands have the same effect on the part. Unless specifically noted, NOP will
represent both NOP and DESL command in later descriptions.
READ, READA, WRIT, and WRITA commands should only be issued after the corresponding bank has
been activated (ACTV command). Refer to STATE DIAGRAM.
ACTV command should only be asserted after corresponding bank has been precharged (PRE or PALL
command).
Required after power up. Refer to POWER-UP INITIALIZATION in page 19.
MRS command should only be issued after all banks have been precharged (PRE or PALL command).
Refer to STATE DIAGRAM.
D a t a S h e4eUt. c o m
www.DataSheet4U.com
5
www.DataSheet4U.com
5 Page 
www.DataSheet4U.com
MB81F161622C-60/-70/-80/-80L
(Continued)
Current
State
CS RAS CAS WE
Addr
Command
Function
Notes
Refreshing H X X X
X
DESL
NOP (Idle after tRC)
L HHX
X
NOP/BST NOP (Idle after tRC)
LHLX
X
READ/READA/
WRIT/WRITA
Illegal
L LHX
X
ACTV/PRE/
PALL
Illegal
LLLX
X
REF/SELF/
MRS
Illegal
Mode
Register
Setting
HXXX
L HHH
X
X
DESL
NOP
NOP (Idle after tRSC)
NOP (Idle after tRSC)
L HH L
X
BST
Illegal
LHLX
X
READ/READA/
WRIT/WRITA
Illegal
ACTV/PRE/
L LXX
X
PALL/REF/ Illegal
SELF/MRS
ABBREVIATIONS:
RA = Row Address
CA = Column Address
BA = Bank Address
AP = Auto Precharge
Notes: *1.
*2.
*3.
*4.
*5.
*6.
*7.
All entries assume the CKE was High during the proceeding clock cycle and the current clock cycle.
Illegal means don’t used command. If used, power up sequence be asserted after power shout down.
Illegal to bank in specified state; entry may be legal in the bank specified by BA, depending on the
state of that bank.
Illegal if any bank is not idle.
Must satisfy bus contention, bus turn around, and/or write recovery requirements.
Refer to TIMING DIAGRAM - 11 & - 12.
NOP to bank precharging or in idle state. May precharge bank specified by BA (and AP).
SELF command should only be issued after the last read data have been appeared on DQ.
MRS command should only be issued on condition that all DQ are in Hi-Z.
DataSheet4 U .com
www.DataSheet4U.com
11
www.DataSheet4U.com
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MB81F161622C.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MB81F161622B | 2 x 512K x 16-Bit SDRAM | Fujitsu |
| MB81F161622C | 2 x 512K x 16-Bit SDRAM | Fujitsu |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |