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ST90E158 Schematic ( PDF Datasheet ) - ST Microelectronics

Teilenummer ST90E158
Beschreibung 8/16-BIT MCU FAMILY WITH UP TO 64K ROM/OTP/EPROM AND UP TO 2K RAM
Hersteller ST Microelectronics
Logo ST Microelectronics Logo 




Gesamt 30 Seiten
ST90E158 Datasheet, Funktion
www.DataSheet4U.com
ST90158 - ST90135
8/16-BIT MCU FAMILY WITH
UP TO 64K ROM/OTP/EPROM AND UP TO 2K RAM
s Register File based 8/16 bit Core Architecture
with RUN, WFI, SLOW and HALT modes
s 0 - 16 MHz Operation @ 5V±10%, -40°C to
+85°C and 0°C to +70°C Operating
Temperature Ranges
s 0 - 14 MHz Operation @ 3V±10% and 0°C to
+70°C Operating Temperature Range
s Fully Programmable PLL Clock Generator, with
Frequency Multiplication and low frequency,
low cost external crystal
TQFP80
s Minimum 8-bit Instruction Cycle time: 83ns - (@
24 MHz internal clock frequency)
s Minimum 16-bit Instruction Cycle time: 250ns -
(@ 24 MHz internal clock frequency)
s Internal Memory:
– EPROM/OTP/ROM 16/24/32/48/64K bytes
– ROMless version available
– RAM 512/768/1K/1.5K/2K bytes
s Maximum External Memory: 64K bytes
www.DataSheet4U.coms 224 general purpose registers available as
RAM, accumulators or index pointers (register
PQFP80
file)
s 80-pin Plastic Quad Flat Package and 80-pin
Thin Quad Flat Package
s 67 fully programmable I/O bits
s Versatile Development Tools, including
Assembler, Linker, C-compiler, Archiver,
Source Level Debugger and Hardware
Emulators with Real-Time Operating System
s 8 external and 1 Non-Maskable Interrupts
available from Third Parties
s DMA Controller and Programmable Interrupt
Handler
s Single Master Serial Peripheral Interface
s Two 16-bit Timers with 8-bit Prescaler, one
usable as a Watchdog Timer (software and
hardware)
s Three (ST90158) or two (ST90135) 16-bit
Multifunction Timers, each with an 8 bit
prescaler, 12 operating modes and DMA
capabilities
s 8 channel 8-bit Analog to Digital Converter, with
Automatic voltage monitoring capabilities and
external reference inputs
s Two (ST90158) or one (ST90135) Serial
Communication Interfaces with asynchronous,
synchronous and DMA capabilities
s Rich Instruction Set with 14 Addressing modes
s Division-by-Zero trap generation
DEVICE SUMMARY
DEVICE
Program RAM
Memory
(Bytes)
(Bytes) MFT SCI
PACKAGE
16K ROM 512 2 1
ST90135 24K ROM 768 2 1
PQFP 80
32K ROM 1K 2 1
48K ROM 1.5K 3 2
ST90158
64k ROM 2K
3
2
PQFP80/
TQFP80
ST90E158
64K
EPROM
2K
3 2 CQFP80
ST90E158LV
64K
EPROM
2K
3 2 CQFP80
ST90T158 64K OTP 2K 3 2 PQFP80
ST90T158LV 64K OTP 2K
3
2
PQFP80/
TQFP80/
ST90R158 ROMless 2K
3
2
PQFP80/
TQFP80
Rev. 3.0
January 2000
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ST90E158 Datasheet, Funktion
www.DataSheet4U.com
ST90158 - GENERAL DESCRIPTION
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
1.1.2 Power Saving Modes
The ST90158 and ST90135 microcontrollers are
developed and manufactured by STMicroelectron-
ics using a proprietary n-well CMOS process.
Their performance derives from the use of a flexi-
ble 256-register programming model for ultra-fast
context switching and real-time event response.
The intelligent on-chip peripherals offload the ST9
core from I/O and data management processing
tasks allowing critical application tasks to get the
maximum use of core resources. The new-gener-
ation ST9 MCU devices now also support low
power consumption and low voltage operation for
power-efficient and low-cost embedded systems.
1.1.1 ST9+ Core
The advanced Core consists of the Central
Processing Unit (CPU), the Register File, the Inter-
rupt and DMA controller, and the Memory Man-
agement Unit. The MMU allows addressing of up
to 4 Megabytes of program and data mapped into
a single linear space.
To optimize performance versus power consump-
tion, a range of operating modes can be dynami-
cally selected.
Run Mode. This is the full speed execution mode
with CPU and peripherals running at the maximum
clock speed delivered by the Phase Locked Loop
(PLL) of the Clock Control Unit (CCU).
Slow Mode. Power consumption can be signifi-
cantly reduced by running the CPU and the periph-
erals at reduced clock speed using the CPU Pres-
caler and CCU Clock Divider (PLL not used) or by
using the CK_AF external clock.
Wait For Interrupt Mode. The Wait For Interrupt
(WFI) instruction suspends program execution un-
til an interrupt request is acknowledged. During
WFI, the CPU clock is halted while the peripheral
and interrupt controller keep running at a frequen-
cy programmable via the CCU. In this mode, the
power consumption of the device can be reduced
by more than 95% (Low Power WFI).
Four independent buses are controlled by the Halt Mode. When executing the HALT instruction,
Core: a 16-bit memory bus, an 8-bit register data and if the Watchdog is not enabled, the CPU and
bus, an 8-bit register address bus and a 6-bit inter- its peripherals stop operating and the status of the
rupt/DMA bus which connects the interrupt and machine remains frozen (the clock is also
www.DataSheet4U.comDMA controllers in the on-chip peripherals with the stopped). A reset is necessary to exit from Halt
core.
mode.
This multiple bus architecture makes the ST9 fam-
ily devices highly efficient for accessing on and off-
chip memory and fast exchange of data with the
on-chip peripherals.
The general-purpose registers can be used as ac-
cumulators, index registers, or address pointers.
Adjacent register pairs make up 16-bit registers for
addressing or 16-bit processing. Although the ST9
has an 8-bit ALU, the chip handles 16-bit opera-
tions, including arithmetic, loads/stores, and mem-
ory/register and memory/memory exchanges.
1.1.3 system Clock
A programmable PLL Clock Generator allows
standard 3 to 5 MHz crystals to be used to obtain a
large range of internal frequencies up to 24 MHz.
1.1.4 I/O Ports
The I/O lines are grouped into up to nine 8-bit I/O
Ports and can be configured on a bit basis to pro-
vide timing, status signals, an address/data bus for
interfacing to external memory, timer inputs and
outputs, analog inputs, external interrupts and se-
rial or parallel I/O.
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6 Page









ST90E158 pdf, datenblatt
www.DataSheet4U.com
ST90158 - GENERAL DESCRIPTION
PIN DESCRIPTION (Cont’d)
Figure 4. 80-Pin PQFP Pin-Out
80
AD4/P0.4 1
64 P1.2/A10
AD5/P0.5
P1.1/A9
AD6/P0.6
P1.0/A8
VSS
AD7/P0.7
RESET
OSCIN
VDD
AS
VSS
OSCOUT
DS P5.1/SDI
VPP*
P4.0
HW0SW1
P5.3
P4.1
P5.4/T1OUTA/DCD0
INTCLK/P4.2
STOUT /P4.3
ST90158/ST90135
P5.5/T1OUTB/RTS0
P5.6/T3OUTA/DCD1
INT 0/WDO UT/P4.4
P5.7/T3OUTB/RTS1/CK_AF
INT4/P4.5
VDD
INT5/T0OUTB/P4.6
P8.0/T3INA
T0OUTA /P4.7
P8.1/T1INB
P2.0
P8.2/T1OUTA/INT1
www.DataSheet4U.comP2.1
P2.2
P8.3/T1OUTB/INT3
P8.4/T1 INA/W AIT/ WDOUT
P2.3
P8.5/T3INB
P2.4
P8.6/IN T7/T3OUT A
P2.5
P8.7/NM I/T3O UTB
P2.6 24
40 AVSS
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*EPROM or OTP devices only
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