GE28F640J3 Datasheet PDF - Intel Corporation
| Part Number | GE28F640J3 | |
| Description | Intel StrataFlash Memory (J3) | |
| Manufacturers | Intel Corporation | |
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Intel StrataFlash® Memory (J3)
256-Mbit (x8/x16)
Product Features
Datasheet
■ Performance
■ Architecture
— 110/115/120/150 ns Initial Access Speed — Multi-Level Cell Technology: High
— 125 ns Initial Access Speed (256 Mbit
density only)
— 25 ns Asynchronous Page mode Reads
— 30 ns Asynchronous Page mode Reads
(256Mbit density only)
— 32-Byte Write Buffer
—6.8 µs per byte effective
programming time
■ Software
Density at Low Cost
— High-Density Symmetrical 128-Kbyte
Blocks
—256 Mbit (256 Blocks) (0.18µm only)
—128 Mbit (128 Blocks)
—64 Mbit (64 Blocks)
—32 Mbit (32 Blocks)
■ Quality and Reliability
— Operating Temperature:
-40 °C to +85 °C
— Program and Erase suspend support
— 100K Minimum Erase Cycles per Block
— Flash Data Integrator (FDI), Common
— 0.18 µm ETOX™ VII Process (J3C)
Flash Interface (CFI) Compatible
■ Security
— 0.25 µm ETOX™ VI Process (J3A)
■ Packaging and Voltage
— 128-bit Protection Register
— 56-Lead TSOP Package
www.DataSheet4U.com—64-bit Unique Device Identifier
—64-bit User Programmable OTP Cells
— 64-Ball Intel® Easy BGA Package
— Lead-free packages available
— Absolute Protection with VPEN = GND
— Individual Block Locking
— 48-Ball Intel® VF BGA Package (32 and
64 Mbit) (x16 only)
— Block Erase/Program Lockout during
Power Transitions
— VCC = 2.7 V to 3.6 V
— VCCQ = 2.7 V to 3.6 V
Capitalizing on Intel’s 0.25 and 0.18 micron, two-bit-per-cell technology, the Intel StrataFlash® Memory (J3)
device provides 2X the bits in 1X the space, with new features for mainstream performance. Offered in 256-
Mbit (32-Mbyte), 128-Mbit (16-Mbyte), 64-Mbit, and 32-Mbit densities, the J3 device brings reliable, two-bit-
per-cell storage technology to the flash market segment. Benefits include more density in less space, high-speed
interface, lowest cost-per-bit NOR device, support for code and data storage, and easy migration to future
devices.
Using the same NOR-based ETOX™ technology as Intel’s one-bit-per-cell products, the J3 device takes
advantage of over one billion units of flash manufacturing experience since 1987. As a result, J3 components
are ideal for code and data applications where high density and low cost are required. Examples include
networking, telecommunications, digital set top boxes, audio recording, and digital imaging.
By applying FlashFile™ memory family pinouts, J3 memory components allow easy design migrations from
existing Word-Wide FlashFile memory (28F160S3 and 28F320S3), and first generation Intel StrataFlash®
memory (28F640J5 and 28F320J5) devices.
J3 memory components deliver a new generation of forward-compatible software support. By using the
Common Flash Interface (CFI) and the Scalable Command Set (SCS), customers can take advantage of density
upgrades and optimized write capabilities of future Intel StrataFlash® memory devices. Manufactured on Intel®
0.18 micron ETOX™ VII (J3C) and 0.25 micron ETOX™ VI (J3A) process technology, the J3 memory device
provides the highest levels of quality and reliability.
Notice: This document contains information on new products in production. The specifications are
subject to change without notice. Verify with your local Intel sales office that you have the latest
datasheet before finalizing a design.
Order Number: 290667-021
March 2005
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Contents
Revision History
Date of
Revision
Version
Description
07/07/99
-001 Original Version
08/03/99
09/07/99
-002
-003
A0–A2 indicated on block diagram
Changed Minimum Block Erase time,IOL, IOH, Page Mode and Byte Mode
currents. Modified RP# on AC Waveform for Write Operations
12/16/99
-004
Changed Block Erase time and tAVWH
Removed all references to 5 V I/O operation
Corrected Ordering Information, Valid Combinations entries
Changed Min program time to 211 µs
Added DU to Lead Descriptions table
Changed Chip Scale Package to Ball Grid Array Package
Changed default read mode to page mode
Removed erase queuing from Figure 10, Block Erase Flowchart
Added Program Max time
Added Erase Max time
Added Max page mode read current
Moved tables to correspond with sections
Fixed typographical errors in ordering information and DC parameter table
www.DataSheet4U.com03/16/00
-005
Removed VCCQ1 setting and changed VCCQ2/3 to VCCQ1/2
Added recommended resister value for STS pin
Change operation temperature range
Removed note that rp# could go to 14 V
Removed VOL of 0.45 V; Removed VOH of 2.4 V
Updated ICCR Typ values
Added Max lock-bit program and lock times
Added note on max measurements
06/26/00
-006
Updated cover sheet statement of 700 million units to one billion
Corrected Table 10 to show correct maximum program times
Corrected error in Max block program time in section 6.7
Corrected typical erase time in section 6.7
2/15/01
-007
Updated cover page to reflect 100K minimum erase cycles
Updated cover page to reflect 110 ns 32M read speed
Removed Set Read Configuration command from Table 4
Updated Table 8 to reflect reserved bits are 1-7; not 2-7
Updated Table 16 bit 2 definition from R to PSS
Changed VPENLK Max voltage from 0.8 V to 2.0 V, Section 6.4, DC
Characteristics
Updated 32Mbit Read Parameters R1, R2 and R3 to reflect 110ns, Section 6.5,
AC Characteristics–Read-Only Operations (1,2)
Updated write parameter W13 (tWHRL) from 90 ns to 500 ns, Section 6.6, AC
Characteristics–Write Operations
Updated Max. Program Suspend Latency W16 (tWHRH1) from 30 to 75 µs,
Section 6.7, Block Erase, Program, and Lock-Bit Configuration Performance
(1,2,3)
04/13/01
-008 Revised Section 7.0, Ordering Information
Datasheet
5
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