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PDF DQ8020 Data sheet ( Hoja de datos )
| Número de pieza | DQ8020 | |
| Descripción | MCC Manchester Code Converter Manual | |
| Fabricantes | LSI Logic | |
| Logotipo |  |
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80820200
MCCTM Manchester
Code Converter
89305
Features
s Compatible with IEEE 802.3 /Ethernet (10BASE5),
IEEE802.3/Cheapernet (10BASE2) and Ethernet
Rev. 1 Specifications
s Compatible with 8003 ELDC®, 8005 Advanced
EDLC
s Manchester Data Encoding/Decoding and
Receiver Clock Recovery with Phase Locked
Loop (PLL)
s Receiver and Collision Squelch Circuit and Noise
Rejection Filter
s Differential TRANSMIT Cable Driver
s Loopback Capability for Diagnostics and
Isolation
s Fail-Safe Watchdog Timer Circuit to Prevent
Continuous Transmission
s 20 MHz Crystal Oscillator
s Transceiver Interface High Voltage (16 V)
Short Circuit Protection
Note: Check for latest Data Sheet revision
before starting any designs.
SEEQ Data Sheets are now on the Web, at
www.lsilogic.com.
This document is an LSI Logic document. Any
reference to SEEQ Technology should be
considered LSI Logic.
s Low Power CMOS Technology with Single 5V
Supply
s 20 pin DIP & PLCC Packages
Description
The SEEQ 8020 Manchester Code Converter chip pro-
vides the Manchester data encoding and decoding func-
tions of the Ethernet Local Area Network physical layer. It
interfaces to the SEEQ 8003 and 8005 Controllers and any
standard Ethernet transceiver as defined by IEEE 802.3
and Ethernet Revision 1.
Functional Block Diagram
TxEN
TxC
TxD
LPBK/
WDTD
CSN
X1
X2
RxC
RxD
COLL
WATCHDOG
TIMER
ENCODER
XTAL
CLOCK
CARRIER
SENSE
DECODER
10MHz
DETECTOR
TRANSMIT
MUX
RECEIVE
COLLISION
Figure 1. 8020 MCC Manchester Code Converter
Block Diagram.
MCC is a trademark of SEEQ Technology Inc.
wwEwD.LDCaistaarSeghiseteeret4d tUra.dceommark of SEEQ Technology Inc.
Pin Configuration
DUAL-IN LINE
TOP VIEW
Tx+
Tx–
VCC
VSS
MODE 1
Rx+
Rx–
MODE 1
GND
1
2
20 V CC
19 Tx+
LPBK/WDTD 3
18 Tx–
Rx+ 4
17 TxD
Rx–
CSN
5
6
8020
16
15
TxC
TxEN
COLL 7
14 X1
RxC 8
13 X2
RxD 9
12 COLL+
VSS 10
11 COLL–
PLASTIC LEADED CHIP CARRIER
TOP VIEW
COLL+
COLL–
3 2 1 20 19
Rx+ 4
Rx– 5
CSN 6
COLL 7
RxC 8
18 Tx–
17 TxD
16 TxC
15 TxEN
14 X1
9 10 11 12 13
MD400023/D
1
1 page  
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8020
LPBK/WDTD Loopback /Watchdog Timer
Disable (Input):
Normal Operation: For normal operation this pin should
be HIGH or tied to VCC. In normal operation the watchdog
timer is enabled.
Loopback: When this pin is brought low, the Manchester
encoded transmit data from TxD and TxC is routed through
the receiver circuit and sent back onto the RxD and RxC
Pins. During loopback, Collision and Receive data inputs
are ignored. The transmit pair is idled. At the end of
transmission, the signal quality error test (SQET) will be
simulated by asserting collision during the inhibit window.
During loopback, the watchdog timer is enabled.
Watchdog Timer Disable: When this pin is between 10 V
(Min.) and 16 V (Max.), the on chip 25 ms Watchdog Timer
will be disabled. The watchdog timer is used to monitor the
transmit enable pin. If TxEN is asserted for too long, then
the watchdog timer (if enabled) will automatically deassert
CSN and inhibit any further transmissions on the Tx+ and
Tx- lines. The watchdog timer is automatically reset each
time TxEN is deasserted.
Interconnection to a Data Link
Controller
Figure 5 shows the interconnections between the 8020
MCC and SEEQ’s 8003 or 8005. There are three connec-
tions for each of the two transmission channels, transmit
and receive, plus the Collision Signal line (COLL).
Transmitter connections are:
Transmit Data, TxD
Transmit Clock, TxC
Transmit Enable, TxEN
Collision, COLL
Receiver connections are:
Receive Data, RxD
Receive Clock, RxC
Carrier Sense, CSN
D.C. and A.C. Characteristics and
Timing
Crystal Specification
Resonant Frequency (CL = 20 pF) ..................... 20 MHz
± 0.005% 0-70° C
and ± 0.003% at 25° C
Type .................................................Fundamental Mode
Circuit .............................................. Parallel Resonance
Load Capacitance (CL) ........................................... 20pF
Shunt Capacitance (CO) ................................... 7pF Max.
Equivalent Series Resistance (R1) ................. 25 Ω Max.
Motional Capacitance (C1) ........................ 0.02 pF Max.
Drive Level ............................................................. 2mW
TxD
TxC
TxEN
LOOPBACK [1]
8003
OR
8005
COLL
RxD
RxC
CSN
TxD
TxC
TxEN
LOOPBACK
8020
MCC
COLL
RxD
RxC
CSN
Figure 5. Interconnection of 8020 and 8003/8005
NOTE
1. Loopback output on 8005 only.
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MD400023/D
5
R1 C1 L1
C0
EQUIVALENT CIRCUIT OF CRYSTAL
Figure 6.
5 Page 
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RxC
Rx(+)
Rx(–)
(LAST BIT = 0)
t29
(–)
(+)
CSN
RxD
t27
(+)
(–)
t23A
t32
t23B
t22
"1" "0"
t30
Figure 10. Receive Timing-End of Packet
8020
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MD400023/D
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| PDF Descargar | [ Datasheet DQ8020.PDF ] | |
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