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D74HC138C Schematic ( PDF Datasheet ) - ETC

Teilenummer D74HC138C
Beschreibung CD74HC138C
Hersteller ETC
Logo ETC Logo 




Gesamt 7 Seiten
D74HC138C Datasheet, Funktion
Data sheet acquired from Harris Semiconductor
SCHS147A
October 1997 - Revised February 1999
CD74HC138, CD74HCT138,
CD74HC238, CD74HCT238
High Speed CMOS Logic 3-to-8 Line Decoder/
Demultiplexer Inverting and Non-Inverting
Features
[ /Title
(CD74
HC138
• Select One Of Eight Data Outputs
Active Low for 138, Active High for 238
• l/O Port or Memory Selector
• Three Enable Inputs to Simplify Cascading
, • Typical Propagation Delay
CwwDw7.D4ataSheet4U.CcoLm= 15pF, TA = 25oC
of
13ns
at
VCC
=
5V,
HCT13
8,
CD74
HC238
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
,
CD74
HCT23
8)
/Sub-
ject
(High
Speed
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
Pinout
CD74HC138, CD74HCT138, CD74HC238, CD74HCT238
(PDIP, SOIC)
TOP VIEW
A0 1
A1 2
A2 3
E1 4
E2 5
E3 6
(Y7) Y7 7
GND 8
16 VCC
15 Y0 (Y0)
14 Y1 (Y1)
13 Y2 (Y2)
12 Y3 (Y3)
11 Y4 (Y4)
10 Y5 (Y5)
9 Y6 (Y6)
Signal names in parentheses are for ’HC238 and ’HCT238.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 1999, Texas Instruments Incorporated
1






D74HC138C Datasheet, Funktion
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER
Enable to Output
HC/HCT138
TEST
25oC
SYMBOL CONDITIONS VCC (V) MIN TYP MAX
tPLH, tPHL CL = 50pF
2 - - 150
4.5 - - 30
-40oC TO
85oC
-55oC TO 125oC
MIN MAX MIN MAX UNITS
- 190 -
265 ns
- 38
-
53 ns
6
- - 26 - 33 -
45 ns
Output Transition Time
(Figure 1)
tTLH, tTHL CL = 50pF
2 - - 75 - 95 - 110 ns
4.5 - - 15 - 19 -
22 ns
6
- - 13 - 16 -
19 ns
Power Dissipation
www.DataSheet4UC.acpoamcitance, (Notes 5, 6)
CPD CL = 15pF
5 - 67 - - - -
- pF
Input Capacitance
HCT TYPES
Propagation Delay
Address to Output
Enable to Output
HC/HCT138
CIN
-
-
- - 10 - 10 -
10 pF
tPLH, tPHL CL = 50pF
CL = 15pF
tPLH, tPHL CL = 50pF
4.5 - - 35 - 44 -
5 - 14 - - - -
4.5 - - 35 - 44 -
53 ns
- ns
53 ns
Enable to Output
HC/HCT238
tPLH, tPHL CL = 15pF
4.5 - - 40 - 50 -
60 ns
Output Transition Time
(Figure 2)
tTLH, tTHL CL = 50pF
4.5 - - 15 - 19 -
22 ns
Power Dissipation
Capacitance, (Notes 5, 6)
CPD CL = 15pF
5 - 67 - - - -
- pF
Input Capacitance
CIN - - - - 10 - 10
NOTES:
5. CPD is used to determine the dynamic power consumption, per gate.
6. PD = VCC2 fi (CPD + CL) where: fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
-
10 pF
Test Circuits and Waveforms
tr = 6ns
INPUT
90%
50%
10%
tf = 6ns
VCC
GND
tTHL
INVERTING
OUTPUT
tPHL
tTLH
90%
50%
10%
tPLH
FIGURE 7. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
tr = 6ns
INPUT
2.7V
1.3V
0.3V
tf = 6ns
3V
GND
tTHL
INVERTING
OUTPUT
tPHL
tTLH
90%
1.3V
10%
tPLH
FIGURE 8. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
6

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