PDF VT1621M Data sheet ( Hoja de datos )

Número de pieza	VT1621M
Descripción	TV Encoder
Fabricantes	VIA
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No Preview Available ! ( DataSheet : www.DataSheet4U.com ) VT1621 and VT1621M TV Encoder Revision 1.0 June 17, 2002 VIA TECHNOLOGIES, INC. www.DataSheet4U.com 1 page TecWhne oCloognnieecst, Inc. VT1621 / VT1621M TV Encoder POWER SUPPLY CURRENT AND TOTAL POWER CONSUMPTION SPECIFICATIONS....................................................................35 DC SPECIFICATIONS....................................................................................................................................................................35 DAC DC CHARACTERISTICS ......................................................................................................................................................36 DAC AC CHARACTERISTICS ......................................................................................................................................................36 DISPLAY SIGNAL CHARACTERISTICS..........................................................................................................................................37 PLL CHARACTERISTICS..............................................................................................................................................................37 PACKAGE MECHANICAL SPECIFICATIONS ........................................................................................................................38 LIST OF FIGURES FIGURE 1. FUNCTIONAL BLOCK DIAGRAM..........................................................................................................................2 FIGURE 2. PIN DIAGRAM (TOP VIEW) .....................................................................................................................................3 FIGURE 3. MASTER CLOCK MODE 1......................................................................................................................................14 FIGURE 4. MASTER CLOCK MODE 2......................................................................................................................................15 FIGURE 5. SLAVE CLOCK MODE ............................................................................................................................................15 FIGURE 6. INPUT INTERFACE PROTOCOL ..........................................................................................................................16 FIGURE 7. INTERLACED 525-LINE (NTSC) VIDEO TIMING..............................................................................................18 FIGURE 8. INTERLACED 525-LINE (PAL-M) VIDEO TIMING ...........................................................................................19 FIGURE 9. INTERLACED 625-LINE (PAL-B, D, G, H, I, NC) VIDEO TIMING (FIELDS 1-4)..........................................20 FIGURE 10. INTERLACED 625-LINE (PAL-B, D, G, H, I, NC) VIDEO TIMING (FIELDS 5-8)........................................21 FIGURE 11. INTERLACED 625-LINE (PAL-N) VIDEO TIMING (FIELDS 1-4)..................................................................22 FIGURE 12. INTERLACED 625-LINE (PAL-N) VIDEO TIMING(FIELDS 5-8)...................................................................23 FIGURE 13. 525-LINE (NTSC/PAL-M) Y (LUMA) VIDEO TEST PATTERN WAVEFORM .............................................24 FIGURE 14. 625-LINE (PAL-B, D, G, H, I, N, NC) Y (LUMA) TEST PATTERN WAVEFORM.........................................24 FIGURE 15. 525-LINE (NTSC/PAL-M) C (CHROMA) VIDEO TEST PATTERN WAVEFORM.......................................25 FIGURE 16. 625-LINE (PAL-B, D, G, H, I, N, NC) C (CHROMA) VIDEO TEST PATTERN WAVEFORM ....................25 FIGURE 17. COMPOSITE 525-LINE (NTSC/PAL-M) VIDEO TEST PATTERN WAVEFORM........................................26 FIGURE 18. COMPOSITE 625-LINE (PAL-B, D, G, H, I, N,NC) VIDEO TEST PATTERN WAVEFORM ......................26 FIGURE 19. LUMINANCE LOWPASS FILTER RESPONSE (27 MHZ)................................................................................30 FIGURE 20. CHROMINANCE LOWPASS FILTER RESPONSE (27MHZ) ..........................................................................31 FIGURE 21. GROUND PLANE WITH 4 LAYER PCB..............................................................................................................33 FIGURE 22. MECHANICAL SPECIFICATION – 44-PIN TQFP THIN QUAD FLAT PACK .............................................38 LIST OF TABLES TABLE 1. PIN LIST (ALPHABETICAL ORDER) .......................................................................................................................4 TABLE 2. PIN DESCRIPTIONS .....................................................................................................................................................5 TABLE 3. REGISTER SUMMARY................................................................................................................................................6 TABLE 4. INPUT DATA FORMAT .............................................................................................................................................17 TABLE 5. DISPLAY MODES FOR PAL (M)..............................................................................................................................27 TABLE 6. DISPLAY MODES FOR NTSC (M, J) & PAL (B, D, G, H, I, N, NC) ....................................................................29 TABLE 7. CLOCK SETTINGS .....................................................................................................................................................32 Revision 1.0 June 17, 2002 -iii- Table of Contents 5 Page TecWhne oCloognnieecst, Inc. REGISTERS Register Overview The following tables summarize the configuration and I/O registers that apply to the VT1621 and VT1621M TV Encoder. These tables also document the power-on default value (“Default”) and access type (“Acc”) for each register. Access type definitions used are RW (Read/Write), RO (Read/Only), “—” for reserved / used (essentially the same as RO), and RWC (or just WC) (Read / Write 1’s to Clear individual bits). Registers indicated as RW may have some read/only bits that always read back a fixed value (usually 0 if unused); registers designated as RWC or WC may have some read-only or read write bits (see individual register descriptions for details). Detailed register descriptions are provided in the following section of this document. All offset and default values are shown in hexadecimal unless otherwise indicated. VT1621 / VT1621M TV Encoder Table 3. Register Summary Offset TV Encoder Registers 00 Input Frame Format 01 Input Sync Format 02 Scaling / Chroma Filter 03 Luma Filter 04 Output Mode 05 Control 1 06 Control 2 07 Start Active Video 08 Start Horizontal Position 09 Start Vertical Position 0A Cr Amplitude Factor 0B Black Level 0C Luma Amplitude Factor 0D Cb Amplitude Factor 0E Power Management 0F Status 10 Special Effect 0 11 Special Effect 1 12 PLL P2 Value 13 PLL D Value 14 PLL N Value 15 PLL Overflow 16 Sub-carrier Value 0 17 Sub-carrier Value 1 18 Sub-carrier Value 2 19 Sub-carrier Value 3 1A - reserved - 1B Version ID 1C Overflow 1D Test 0 1E Test 1 1F Test 2 20 TV Sync Step 21 TV Burst Envelope Step 22 TV Sub-carrier Phase Adjustment 23 TV Blank Level 24 TV Signal Overflow 25-49 - reserved - 4A Input Aperture Threshold 4B Input Aperture Delta 4C Aperture Upper Threshold 4D Aperture Lower Threshold 4E Aperture Mode and Delta 4F Coring Function 50 Y Delay Control 51 UV Delay Control 52 Burst Maximum Amplitude 53-FF - reserved - Default Acc 00 RW 00 RW 00 RW 00 RW 00 RW 00 RW 00 RW 00 RW 00 RW 00 RW 00 RW 00 RW 00 RW 00 RW 00 RW 00 RO 00 RW 00 RW 00 RW 05 RW 21 RW 04 RW 00 RW 00 RW 00 RW 00 RW 00 – 02 RO 00 RW 00 RW 00 RW 00 RW 00 RW 00 RW 00 RW 00 RW 00 RW 00 – 00 RW 00 RW 00 RW 00 RW 00 RW 00 RW 00 RW 00 RW 00 RW 00 – Revision 1.0 June 17, 2002 -6- Register Descriptions 11 Page

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