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VT1621 Schematic ( PDF Datasheet ) - VIA

Teilenummer VT1621
Beschreibung TV Encoder
Hersteller VIA
Logo VIA Logo 




Gesamt 30 Seiten
VT1621 Datasheet, Funktion
( DataSheet : www.DataSheet4U.com )
VT1621 and VT1621M
TV Encoder
Revision 1.0
June 17, 2002
VIA TECHNOLOGIES, INC.
www.DataSheet4U.com






VT1621 Datasheet, Funktion
TecWhne oCloognnieecst, Inc.
VT1621 / VT1621M TV Encoder
VT1621 and VT1621M
TV Encoder
PRODUCT FEATURES
TV output supporting inputs up to 800x600 graphics resolutions
Supports digital RGB (15/16 or 24-bit) or YCrCb (CCIR601 or CCIR656) 16 bit 4:2:2 input video
data in both interlaced or non-interlaced formats
Supports NTSC(M and J) or PAL (B, D, G, H, I, M, N and Nc) TV output standards
Supports Macrovision 7.1 anti-copy protection (VT1621M only)
Underflow check and coring function for reducing the input noise
Composite, S-Video and SCART output support
Flicker filtering to enhance to TV image quality
Dot crawl control circuit to still this phenomenon
Master or slave video timing operation
New Algorithm for text sharpness
High Quality 3 x 9-bit Video DAC
Serial bus programming interface
Programmable power management
Automatic detection of TV presence
Buffered crystal clock output pin
ProScaleengine support for underscan and overscan mode
44-pin TQFP package
Revision 1.0 June 17, 2002
-1-
Product Features

6 Page









VT1621 pdf, datenblatt
TecWhne oCloognnieecst, Inc.
Register Descriptions
VT1621 / VT1621M TV Encoder
Offset 00 – Input Frame Format ..................................... RW
7-5 Frame Resolution
000 512x384................................................. default
001 720x400
010 640x400
011 640x480
100 800x600
* 101 720x576 (for PAL)
* 101 720x480 (for NTSC)
* 110 800x500 (for PAL)
* 110 640x400 (for NTSC)
111 -reserved-
* interlaced input mode
4 RGB Pass through Mode
0 Disable................................................... default
1 Enable
3-0 Input Data Format
00xx -reserved-................................. default = 0000b
0100 12-bit multiplexed RGB (24-bit color) input
(“C” multiplex scheme)
0101 12-bit multiplexed RGB (24-bit color) input
(“I” multiplex scheme)
0110 8-bit multiplexed RGB (24-bit color) input
0111 8-bit multiplexed RGB (16-bit color) input
1000 8-bit multiplexed RGB (15-bit color) input
1001 8-bit multiplexed YCrCb (Normal) input (Y,
Cr and Cb multiplexed)
101x 8-bit multiplexed YCrCb (Cr and Cb shift 128)
input (Y, Cr and Cb multiplexed)
110x 8-bit multiplexed YCrCb (Y shift 16) input (Y,
Cr and Cb multiplexed)
111x 8-bit multiplexed YCrCb (Y shift 16 and Cr
and Cb shift 128) input (Y, Cr and Cb
multiplexed)
Offset 01 – Input Sync Format......................................... RW
7 Reserved ........................................always reads 0
6 Field Signal Polarity
0 Active Low ............................................default
1 Active High
5 DS_BCO Pin Control
0 BCO Output ...........................................default
1 DS Input
4 Detect Embedded Sync
0 Don’t detect............................................default
1 Sync will be detected from the embedded
codes on the pixel input stream
3 Vertical Sync Direction
0 Input ....................................................default
1 Output
2 Horizontal Sync Direction
0 Input ....................................................default
1 Output
1 Vertical Sync Polarity
0 Active Low ............................................default
1 Active High
0 Horizontal Sync Polarity
0 Active Low ............................................default
1 Active High
Revision 1.0 June 17, 2002
-7-
Register Descriptions

12 Page





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