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PDF CS8427 Data sheet ( Hoja de datos )
| Número de pieza | CS8427 | |
| Descripción | 96 kHz Digital Audio Interface Transceiver | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CS8427 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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CS8427
96 kHz Digital Audio Interface Transceiver
Features
Complete EIAJ CP1201, IEC-60958, AES3,
S/PDIF-compatible Transceiver
+5.0 V Analog Supply (VA+)
+3.3 V or +5.0 V Digital Interface (VL+)
Flexible 3-wire Serial Digital I/O Ports
Adjustable Sample Rate up to 96 kHz
Low-jitter Clock Recovery
Pin and Microcontroller Read/Write Access to
Channel Status and User Data
Microcontroller and Standalone Modes
Differential Cable Driver and Receiver
On-chip Channel Status and User Data Buffer
Memories Permit Block Reads & Writes
OMCK System Clock Mode
Decodes Audio CD Q Sub-code
General Description
The CS8427 is a stereo digital audio transceiver with
AES3 and serial digital audio inputs, AES3 and serial
digital audio outputs, and includes comprehensive con-
trol ability through a 4-wire microcontroller port. Channel
status and user data are assembled in block-sized buff-
ers, making read/modify/write cycles easy.
A low-jitter clock recovery mechanism yields a very clean
recovered clock from the incoming AES3 stream.
Target applications include A/V receivers, CD-R, DVD
receivers, multimedia speakers, digital mixing consoles,
effects processors, set-top boxes, and computer and au-
tomotive audio systems.
The CS8427 is available in 28-pin SOIC and TSSOP
packages in Commercial (-10°C to +70°C) and Automo-
tive (-40°C to +85°C) grades. The CDB8427 Customer
Demonstration Board is also available for device evalu-
ation and implementation suggestions. Please see
“Ordering Information” on page 49 for complete details.
I
VA+ AGND FILT RERR RMCK
VL+ DGND
ILRCK
ISCLK
SDIN
Serial
Audio
Input
Serial
Audio
Output
OLRCK
OSCLK
SDOUT
RXP
RXN
Receiver
Clock &
Data
Recovery
AES3
S/PDIF
Decoder
C & U bit
Data
Buffer
AES3
S/PDIF
Encoder
Driver
TXP
TXN
Misc.
Control
Control
Port &
Registers
Output
Clock
Generator
H/S RST
EMPH U TCBL SDA/ SCL/ AD1/ AD0/ INT
CDOUT CCLK CDIN CS
OMCK
www.cirrus.com
Copyright Cirrus Logic, Inc. 2010
(All Rights Reserved)
MAY ‘10
DS477F5
1
1 page  
CS8427
1. CHARACTERISTICS AND SPECIFICATIONS
All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical per-
formance characteristics and specifications are derived from measurements taken at nominal supply voltages and
TA = 25°C.
SPECIFIED OPERATING CONDITIONS
AGND, DGND = 0 V, all voltages with respect to 0 V.
Parameter
Power Supply Voltage
Ambient Operating Temperature:
(Note 1)
‘-CS’, ‘CSZ’ & ‘-CZ’
‘-DS’ & ‘-DZ’
Symbol
VA+
VL+
TA
Min
4.5
2.85
-10
-40
Typ
5.0
3.3 or 5.0
-
-
Max
5.5
5.5
+70
+85
Units
V
V
°C
Notes: 1. I²C protocol is supported only in VL+ = 5.0 V mode.
ABSOLUTE MAXIMUM RATINGS
AGND, DGND = 0 V; all voltages with respect to 0 V. Operation beyond these limits may result in permanent dam-
age to the device. Normal operation is not guaranteed at these extremes.
Parameter
Symbol
Min
Max Units
Power Supply Voltage
VL+,VA+
-
6.0 V
Input Current, Any Pin Except Supplies
Input Voltage
Ambient Operating Temperature (power applied)
Storage Temperature
(Note 2)
Iin
Vin
TA
Tstg
- ±10 mA
-0.3 (VL+) + 0.3 V
-55 125 °C
-65 150 °C
Notes: 2. Transient currents of up to 100 mA will not cause SCR latch-up.
DS477F5
5
5 Page 
2. TYPICAL CONNECTION DIAGRAM
CS8427
+5.0 V
Analog
Supply*
Ferrite *
Bead
0.1μF
0.1μF
+3.3 V or +5.0 V
Digital Supply
AES3/
SPDIF
Source
Cable
Termination
3-wire Serial
Audio Source
VA+
RXP
RXN
VL+
TXP
TXN
CS8427
ILRCK
ISCLK
SDIN
OLRCK
OSCLK
SDOUT
Clock Source
and Control
Hardware
Control
To other
CS8427's
RMCK
SDA/CDOUT
OMCK
AD0/CS
SCL/CCLK
AD1/CDIN
INT
EMPH/AD 2
RERR
U
RST
TCBL
H/S
AGND FILT
DGND
RFILT
CFILT CRIP
Cable
Interface
AES3/
SPDIF
Equipment
3-wire Serial
Audio Input
Device
Microcontroller
* A separate analog supply is only necessary in applications where RMCK is used
for a jitter sensitive task. For applications where RMCK is not used for a jitter
sensitive task, connect VA+ to VD+ via a ferrite bead. Keep the decoupling
capacitor between VA+ and AGND.
DS477F5
Figure 5. Recommended Connection Diagram for Software Mode
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CS8427.PDF ] | |
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