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GVT7C1355A Schematic ( PDF Datasheet ) - Cypress Semiconductor

Teilenummer GVT7C1355A
Beschreibung (GVT7xxxx) 256K x 36 / 512K x 18 Flow Thru SRAM
Hersteller Cypress Semiconductor
Logo Cypress Semiconductor Logo 




Gesamt 30 Seiten
GVT7C1355A Datasheet, Funktion
( DataSheet : www.DataSheet4U.com )
1CY7C1357A
CY7C1355A/GVT71256ZB36
PRELIMINARY CY7C1357A/GVT71512ZB18
256Kx36/512Kx18 Flow-Thru SRAM with NoBL™ Architecture
Features
• Zero Bus Latency, no dead cycles between write and
read cycles
• Fast clock speed: 133, 117, and 100 MHz
• Fast access time: 6.5, 7.0, 7.5, and 8.0 ns
• Internally synchronized registered outputs eliminate
the need to control OE
• Single 3.3V –5% and +5% power supply VCC
• Separate VCCQ for 3.3V or 2.5V I/O
• Single R/W (READ/WRITE) control pin
• Positive clock-edge triggered, address, data, and con-
trol signal registers for fully pipelined applications
• Interleaved or linear 4-word burst capability
• Individual byte write (BWa–BWd) control (may be tied
LOW)
• CKE pin to enable clock and suspend operations
• Three chip enables for simple depth expansion
• SNOOZE MODE for low power standby
• JTAG boundary scan
• Low profile 119-bump, 14-mm x 22-mm BGA (Ball Grid
Array) and 100-pin TQFP packages
Functional Description
The CY7C1355A/GVT71256ZB36 and CY7C1357A/
GVT71512ZB18 SRAMs are designed to eliminate dead cy-
cles when transitions from READ to WRITE or vice versa.
These SRAMs are optimized for 100 percent bus utilization
and achieves Zero Bus Latency (ZBL)/No Bus Latency (No-
BL). They integrate 262,144x36 and 524,288x18 SRAM cells,
respectively, with advanced synchronous peripheral circuitry
and a 2-bit counter for internal burst operation. These employ
high-speed, low power CMOS designs using advanced triple-
layer polysilicon, double-layer metal technology. Each memory
cell consists of four transistors and two high valued resistors.
All synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, depth-expansion
Chip Enables (CE, CE2, and CE2), Cycle Start Input (ADV/LD),
Clock Enable (CKE), Byte Write Enables (BWa, BWb, BWc,
and BWd), and read-write control (R/W). BWc and BWd apply
to CY7C1355A/GVT71256ZB36 only.
Address and control signals are applied to the SRAM during
one clock cycle, and one cycle later, its associated data oc-
curs, either read or write.
A Clock Enable (CKE) pin allows operation of the
CY7C1355A/CY7C1357A/GVT71256ZB36/GVT71512ZB18
to be suspended as long as necessary. All synchronous inputs
are ignored when (CKE) is HIGH and the internal device reg-
isters will hold their previous values.
There are three Chip Enable pins (CE, CE2, CE2) that allow
the user to deselect the device when desired. If any one of
these three are not active when ADV/LD is LOW, no new mem-
ory operation can be initiated and any burst cycle in progress
is stopped. However, any pending data transfers (read or write)
will be completed. The data bus will be in high-impedance
state one cycle after chip is deselected or a write cycle is initi-
ated.
The CY7C1355A/GVT71256ZB36 and CY7C1357A/
GVT71512ZB18 have an on-chip 2-bit burst counter. In the
burst mode, the CY7C1355A/GVT71256ZB36 and
CY7C1357A/GVT71512ZB18 provide four cycles of data for a
single address presented to the SRAM. The order of the burst
sequence is defined by the MODE input pin. The MODE pin
selects between linear and interleaved burst sequence. The
ADV/LD signal is used to load a new external address
(ADV/LD=LOW) or increment the internal burst counter
(ADV/LD=HIGH)
Output Enable (OE), Snooze Enable (ZZ) and burst sequence
select (MODE) are the asynchronous signals. OE can be used
to disable the outputs at any given time. ZZ may be tied to LOW
if it is not used.
Four pins are used to implement JTAG test capabilities. The
JTAG circuitry is used to serially shift data to and from the
device. JTAG inputs use LVTTL/LVCMOS levels to shift data
during this testing mode of operation.
Selection Guide
7C1355A-133/
71256ZB36-6.5
7C1357A-133/
71512ZB18-6.5
Maximum Access Time (ns)
6.5
Maximum Operating Current (mA)
410
Maximum CMOS Standby Current (mA)
30
No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation.
7C1355A-117/
71256ZB36-7
7C1357A-117/
71512ZB18-7
7
385
30
7C1355A-100/
71256ZB36-7.5
7C1357A-100/
71512ZB18-7.5
7.5
350
30
7C1355A1-100/
71256ZB36-8
7C1357A1-100/
71512ZB18-8
8
350
30
www.DataSheet4U.com
wwwC.yDparteaSshseSete4mU.iccoomnductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
May 24, 2001






GVT7C1355A Datasheet, Funktion
PRELIMINARY
CY7C1355A/GVT71256ZB36
CY7C1357A/GVT71512ZB18
Pin Descriptions (CY7C1355A/GVT71256ZB36) (continued)
256Kx36
TQFP Pins
51, 52, 53,
56–59, 62, 63
68, 69, 72–75,
78, 79, 80
1, 2, 3, 6–9, 12,
13
18, 19, 22–25,
28, 29, 30
38
39
43
256Kx36
PBGA Pins
(a) 6P, 7P, 7N,
6N, 6M, 6L, 7L,
6K, 7K,
(b) 7H, 6H, 7G,
6G, 6F, 6E, 7E,
7D, 6D,
(c) 2D, 1D, 1E,
2E, 2F, 1G, 2G,
1H, 2H,
(d) 1K, 2K, 1L,
2L, 2M, 1N, 2N,
1P, 2P
2U
3U
4U
Name
DQa
DQb
DQc
DQd
TMS
TDI
TCK
Type
Input/
Output
Description
Data Inputs/Outputs: Both the data input path and data output
path are registered and triggered by the rising edge of CLK. Byte
“a” is DQa pins; Byte “b” is DQb pins; Byte “c” is DQc pins; Byte
“d” is DQd pins.
Input
IEEE 1149.1 test inputs. LVTTL-level inputs. If Serial Boundary
Scan (JTAG) is not used, these pins can be floating (i.e., No
Connect) or be connected to VCC.
42 5U TDO
15, 16, 41, 65,
91
5, 10, 14, 17,
21, 26, 40, 55,
60, 66, 67, 71,
76, 90
4, 11, 20, 27,
54, 61, 70, 77
84
4C, 2J, 4J, 6J,
4R
3D, 5D, 3E, 5E,
3F, 5F, 3H, 5H,
3K, 5K, 3M,
5M, 3N, 5N, 3P,
5P, 5R
1A, 7A, 1F, 7F,
1J, 7J, 1M, 7M,
1U, 7U
4A, 1B, 7B, 1C,
7C, 4D, 3J, 5J,
4L, 1R, 7R, 1T,
2T, 6T, 6U
VCC
VSS
VCCQ
NC
Output
Supply
Ground
IEEE 1149.1 test output. LVTTL-level output. If Serial Boundary
Scan (JTAG) is not used, these pins can be floating (i.e., No
Connect).
Power Supply: +3.3V –5% and +5%.
Ground: GND.
I/O Supply Output Buffer Supply: +3.3V –0.165V and +0.165V for 3.3V I/O.
+2.5V –0.125V and +0.4V for 2.5V I/O.
- No Connect: These signals are not internally connected. It can
be left floating or be connected to VCC or to GND.
Pin Descriptions (CY7C1357A/GVT71512ZB18)
512Kx18
TQFP Pins
37,
36,
32, 33, 34, 35,
44, 45, 46, 47,
48, 49, 50, 80,
81, 82, 83, 99,
100
93,
94,
512Kx18
PBGA Pins
4P
4N
2A, 3A, 5A, 6A,
3B, 5B, 6B, 2C,
3C, 5C, 6C, 4G,
2R, 6R, 2T, 3T,
5T, 6T
5L
3G
Name
SA0,
SA1,
SA
BWa,
BWb
Type
Input-
Synchronous
Description
Synchronous Address Inputs: The address register is triggered
by a combination of the rising edge of CLK, ADV/LD LOW, CKE
LOW and true chip enables. SA0 and SA1 are the two least
significant bits of the address field and set the internal burst
counter if burst cycle is initiated.
Input-
Synchronous
Synchronous Byte Write Enables: Each 9-bit byte has its own
active low byte write enable. On load write cycles (when R/W
and ADV/LD are sampled LOW), the appropriate byte write sig-
nal (BWx) must be valid. The byte write signal must also be valid
on each cycle of a burst write. Byte write signals are ignored
when R/W is sampled HIGH. The appropriate byte(s) of data are
written into the device one cycle later. BWa controls DQa pins;
BWb controls DQb pins. BWx can all be tied LOW if always doing
write to the entire 18-bit word.
6

6 Page









GVT7C1355A pdf, datenblatt
PRELIMINARY
CY7C1355A/GVT71256ZB36
CY7C1357A/GVT71512ZB18
1 TEST-LOGIC
RESET
0
0 REUN-TEST/ 1
IDLE
SELECT
DR-SCAN
0
1
CAPTURE-DR
1
0
SHIFT-DR
0
1
EXIT1-DR
1
0
PAUSE-DR
0
1
0
EXIT2-DR
1
UPDATE-DR
1
0
SELECT
IR-SCAN
0
1
CAPTURE-IR
0
SHIFT-IR
1
EXIT1-IR
0
PAUSE-IR
1
0
EXIT2-IR
1
UPDATE-IR
1
0
1
0
1
0
Figure 1. TAP Controller State Diagram[21]
Note:
21. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
12

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