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PDF MT48LC16M16LFFG Data sheet ( Hoja de datos )
| Número de pieza | MT48LC16M16LFFG | |
| Descripción | (MT48xx16x16LFxG) 256M x 16 Mobile SDRAM | |
| Fabricantes | Micron Technology | |
| Logotipo |  |
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PRELIMINARY‡
256Mb: x16
MOBILE SDRAM
MOBILE SDRAM
FEATURES
• Temperature Compensated Self Refresh (TCSR)
• Fully synchronous; all signals registered on
positive edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE and Auto Refresh Modes
• Self Refresh Mode
• 64ms, 8,192-cycle refresh
• LVTTL-compatible inputs and outputs
• Low voltage power supply
• Deep Power Down
• Partial Array Self Refresh power-saving mode
OPTIONS
MARKING
• VDD/VDDQ
3.3V/3.3V
LC
2.5V/2.5V–1.8V
V
1.8V/1.8V
H
• Configurations
16 Meg x 16 (4 Meg x 16 x 4 banks)
16M16
• Plastic Packages – OCPL
54-pinTSOP (400 mil)1
TG
54-pinTSOP (400 mil) Lead-Free1
P
54-ball VFBGA (8mm x 14mm)2
FG
54-ball VFBGA (8mm x 14mm) Lead-Free2 BG
• Timing (Cycle Time)
8.0ns @ CL = 3 (125 MHz)
-8
10ns @ CL = 3 (100 MHz)
-10
• Operating Temperature
Commercial (0oC to + 70oC)
None
Industrial (-40oC to + 85oC)
IT
MT48LC16LFFG, MT48LC16M16LFBG,
MT48V16MLFFG, MT48V16M16LFBG,
MT48H16M16LFFG, MT48H16M16LFBG
4 Meg x 16 x 4 banks
For the latest data sheet revisions, please refer to the Micron
Web site: www.micron.com/dramds
BALL ASSIGNMENT (Top View)
54-Ball VFBGA
123456789
A VSS DQ15 VSSQ
VDDQ DQ0 VDD
B DQ14 DQ13 VDDQ
VSSQ DQ2 DQ1
C DQ12 DQ11 VSSQ
VDDQ DQ4 DQ3
D DQ10 DQ9 VDDQ
VSSQ DQ6 DQ5
E DQ8 NC VSS
VDD LDQM DQ7
F UDQM CK CKE
CAS\ RAS\ WE\
G A12 A11 A9
BA0 BA1 CS\
H A8 A7 A6
A0 A1 A10
J VSS A5 A4
A3 A2 VDD
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
16 Meg x 16
4 Meg x 16 x 4 banks
8K
8K (A0–A12)
4 (BA0, BA1)
512 (A0–A8)
KEY TIMING PARAMETERS
NOTE: 1. Contact Factory for availability.
2. Due to space limitations, FBGA-packaged compo-
nents have an abbreviated part mark that is different
from the part number. See our Web site for more
information on abbreviated component marks.
SPEED
GRADE
-8
-10
-8
-10
-8
-10
CLOCK
FREQUENCY
125 MHz
100 MHz
100 MHz
83 MHz
50 MHz
40 MHz
ACCESS TIME
CL=1* CL=2* CL=3*
– – 7ns
– – 7ns
– 8ns –
– 8ns
–
19ns –
–
22ns –
–
SETUP HOLD
TIME TIME
2.5ns 1.0ns
2.5ns 1.0ns
2.5ns 1.0ns
2.5ns 1.0ns
2.5ns 1.0ns
2.5ns 1.0ns
*CL = CAS (READ) latency
www.DataSheet4U.com
256Mb: x16 Mobile SDRAM
MobileRamY26L_B.p65 – Pub. 04/03
1 ©2003 Micron Technology, Inc. All rights reserved.
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1 page  
FUNCTIONAL BLOCK DIAGRAM
16 Meg x 16 SDRAM
PRELIMINARY
256Mb: x16
MOBILE SDRAM
CKE
CLK
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
MODE REGISTER
12
A0-A12,
BA0, BA1
15
ADDRESS
REGISTER
REFRESH 13
COUNTER
13
ROW-
ADDRESS
MUX
13
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
8192
BANK0
MEMORY
ARRAY
(8,192 x 512 x 16)
SENSE AMPLIFIERS
8192
2
BANK
CONTROL
LOGIC
2
COLUMN-
ADDRESS
9
9 COUNTER/
LATCH
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
512
(x16)
COLUMN
DECODER
22
DATA
16 OUTPUT
REGISTER
DATA
16 INPUT
REGISTER
16
DQML,
DQMH
DQ0-
DQ15
256Mb: x16 Mobile SDRAM
MobileRamY26L_B.p65 – Pub. 04/03
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
5 Page 
PRELIMINARY
256Mb: x16
MOBILE SDRAM
EXTENDED MODE REGISTER
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 All have to be set to "0" DS TCSR PASR
Extended Mode
Register (Ex)
A5 Driver Strength
0 Half Strength
1 Full Strength
A4 A3 Maximum Case Temp
11
00
85˚C
70˚C
01
45˚C
10
15˚C
A2 A1 A0
000
001
010
011
100
101
110
111
Self Refresh Coverage
Four Banks
Two Banks (BA1=0)
One Bank (BA1=BA0=0)
RFU
RFU
Half Bank (BA1=BA0=0)
Quarter Bank (BA1=BA0=0)
RFU
NOTE: 1. E14 and E13 (BA1 and BA0) must be “1, 0” to select the
Extended Mode Register (vs. the base Mode Register).
EXTENDED MODE REGISTER
The Extended Mode Register controls the functions
beyond those controlled by the Mode Register. These
additional functions are special features of the Mobile
device. They include Temperature Compensated Self
Refresh (TCSR), Partial Array Self Refresh (PASR) and
Driver Strength.
The Extended Mode Register is programmed via
the Mode Register Set command (BA1=1,BA0=0) and
retains the stored information until it is programmed
again or the device loses power.
The Extended Mode Register must be programmed
with M6 through M12 set to “0.” The Extended Mode
Register must be loaded when all banks are idle and no
bursts are in progress, and the controller must wait the
specified time before initiating any subsequent op-
eration. Violating these requirements results in un-
specified operation.
TEMPERATURE COMPENSATED SELF REFRESH
Temperature Compensated Self Refresh allows the
controller to program the Refresh interval during SELF
REFRESH mode, according to the case temperature of
the mobile device. This allows great power savings
during SELF REFRESH during most operating tempera-
ture ranges.
Every cell in the DRAM requires refreshing due to
the capacitor losing its charge over time. The refresh
rate is dependent on temperature. At higher tempera-
tures a capacitor loses charge quicker than at lower
temperatures, requiring the cells to be refreshed more
often. Historically, during Self Refresh, the refresh rate
has been set to accommodate the worst case, or highest
temperature range expected.
256Mb: x16 Mobile SDRAM
MobileRamY26L_B.p65 – Pub. 04/03
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MT48LC16M16LFFG.PDF ] | |
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