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NG82925X Schematic ( PDF Datasheet ) - Intel

Teilenummer NG82925X
Beschreibung Express Chipset
Hersteller Intel
Logo Intel Logo 




Gesamt 30 Seiten
NG82925X Datasheet, Funktion
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Intel® 925X Express Chipset
Datasheet
For the Intel® 82925X Memory Controller Hub (MCH)
August 2004
www.DataSheet4U.com
Document Numwbwerw: .D30a1ta4S6h4e-0e0t42U.com






NG82925X Datasheet, Funktion
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8.1.27
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8.1.58
8.1.59
MSI_CAPID—Message Signaled Interrupts Capability ID (D1:F0) .....132
MC—Message Control (D1:F0)...........................................................133
MA—Message Address (D1:F0) .........................................................134
MD—Message Data (D1:F0)...............................................................134
PEG_CAPL—PCI Express* Capability List (D1:F0) ............................135
PEG_CAP—PCI Express*-G Capabilities (D1:F0)..............................135
DCAP—Device Capabilities (D1:F0) ...................................................136
DCTL—Device Control (D1:F0)...........................................................137
DSTS—Device Status (D1:F0)............................................................138
LCAP—Link Capabilities (D1:F0) ........................................................139
LCTL—Link Control (D1:F0)................................................................140
LSTS—Link Status (D1:F0).................................................................141
SLOTCAP—Slot Capabilities (D1:F0) .................................................142
SLOTCTL—Slot Control (D1:F0).........................................................143
SLOTSTS—Slot Status (D1:F0)..........................................................144
RCTL—Root Control (D1:F0) ..............................................................145
RSTS—Root Status (D1:F0) ...............................................................146
PEGLC—PCI Express*-G Legacy Control ..........................................147
VCECH—Virtual Channel Enhanced Capability Header (D1:F0)........148
PVCCAP1—Port VC Capability Register 1 (D1:F0) ............................148
PVCCAP2—Port VC Capability Register 2 (D1:F0) ............................149
PVCCTL—Port VC Control (D1:F0) ....................................................149
VC0RCAP—VC0 Resource Capability (D1:F0)...................................150
VC0RCTL—VC0 Resource Control (D1:F0) .......................................150
VC0RSTS—VC0 Resource Status (D1:F0) ........................................151
VC1RCAP—VC1 Resource Capability (D1:F0)...................................151
VC1RCTL—VC1 Resource Control (D1:F0) .......................................152
VC1RSTS—VC1 Resource Status (D1:F0) ........................................153
RCLDECH—Root Complex Link Declaration Enhanced Capability
Header (D1:F0) ...................................................................................153
ESD—Element Self Description (D1:F0).............................................154
LE1D—Link Entry 1 Description (D1:F0).............................................155
LE1A—Link Entry 1 Address (D1:F0)..................................................156
PEGSSTS—PCI Express*-G Sequence Status (D1:F0).....................156
9 System Address Map.......................................................................................................158
9.1 Legacy Address Range.......................................................................................159
9.1.1 DOS Range (0h – 9_FFFFh)...............................................................160
9.1.2 Legacy Video Area (A_0000h–B_FFFFh) ...........................................160
9.1.3 Expansion Area (C_0000h–D_FFFFh)................................................161
9.1.4 Extended System BIOS Area (E_0000h–E_FFFFh) ...........................162
9.1.5 System BIOS Area (F_0000h–F_FFFFh)............................................162
9.1.6 Programmable Attribute Map (PAM) Memory Area Details.................162
9.2 Main Memory Address Range (1 MB to TOLUD) ...............................................163
9.2.1 ISA Hole (15 MB–16 MB) ....................................................................163
9.2.2 TSEG...................................................................................................164
9.2.3 Pre-allocated Memory .........................................................................164
9.3 PCI Memory Address Range (TOLUD – 4 GB) ..................................................164
9.3.1 APIC Configuration Space (FEC0_0000h-FECF_FFFFh) ..................165
9.3.2 HSEG (FEDA_0000h–FEDB_FFFFh).................................................166
9.3.3 FSB Interrupt Memory Space (FEE0_0000–FEEF_FFFF) .................166
9.3.4 High BIOS Area ...................................................................................166
9.3.5 PCI Express* Configuration Address Space .......................................166
6 Intel® 82925X MCH Datasheet

6 Page









NG82925X pdf, datenblatt
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Intel® 82925X MCH Features
ƒ Processor Interface
ƒ System Memory
One Intel® Pentium® 4 processor (supports
One or two 64-bit wide DDR2 SDRAM data
775-land package)
channels
Supports Pentium 4 processor FSB interrupt Bandwidth up to 8.5 GB/s (DDR2 533) in
delivery
dual-channel Interleaved mode
800 MT/s (200 MHz) FSB
ECC and Non-ECC memory
Supports Hyper-Threading Technology
256-Mb, 512-Mb and 1-Gb DDR2
(HT Technology)
technologies
FSB Dynamic Bus Inversion (DBI)
Only x8, x16, DDR2 devices with four
32-bit host bus addressing for access to
banks and also supports eight bank, 1-Gbit
4 GB of memory space
DDR2 devices.
12-deep In-Order Queue
Opportunistic refresh
1-deep Defer Queue
Up to 64 simultaneously open pages (four
GTL+ bus driver with integrated GTL
ranks of eight bank devices* 2 channels)
termination resistors
SPD (Serial Presence Detect) scheme for
Supports a Cache Line Size of 64 bytes
DIMM detection support
Supports Intel Pentium® 4 processors with
Suspend-to-RAM support using CKE
Intel® EM64T
Supports configurations defined in the
ƒ DMI Interface
JEDEC DDR2 DIMM specification only
A chip-to-chip connection interface to Intel® ƒ PCI Express Graphics Interface
ICH6
One x16 PCI Express port
2 GB/s point-to-point DMI to ICH6 (1 GB/s Compatible with the PCI Express Base
each direction)
Specification Revision 1.0a
100 MHz reference clock (shared with PCI ƒ Package
Express Graphics Attach).
37.5 mm × 37.5 mm., 1210 balls, variable
32-bit downstream addressing
ball pitch
Messaging and Error Handling
12 Intel® 82925X MCH Datasheet

12 Page





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