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PDF ST6252B Data sheet ( Hoja de datos )
| Número de pieza | ST6252B | |
| Descripción | (ST6252B / ST6262B) 8-BIT OTP/EPROM MCUs | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ST6252B (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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ST62T52B
R ST62T62B/E62B
8-BIT OTP/EPROM MCUs WITH
A/D CONVERTER, AUTO-RELOAD TIMER AND EEPROM
s 3.0 to 6.0V Supply Operating Range
s 8 MHz Maximum Clock Frequency
s -40 to +125°C Operating Temperature Range
s Run, Wait and Stop Modes
s 5 Interrupt Vectors
s Look-up Table capability in Program Memory
s Data Storage in Program Memory:
User selectable size
s Data RAM: 128 bytes
s Data EEPROM: 64 bytes (none on ST62T52B)
s User Programmable Options
s 9 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input
s 5 I/O lines can sink up to 20mA to drive LEDs or
TRIACs directly
s 8-bit Timer/Counter with 7-bit programmable
prescaler
s 8-bit Auto-reload Timer with 7-bit programmable
prescaler (AR Timer)
s Digital Watchdog
s 8-bit A/D Converter with 4 analog inputs
s On-chip Clock oscillator can be driven by Quartz
Crystal Ceramic resonator or RC network
s User configurable Power-on Reset
s One external Non-Maskable Interrupt
s ST626x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port)
DEVICE SUMMARY
DEVICE
ST62T52B
ST62T62B
ST62E62B
EPROM
(Bytes)
1836
OTP
(Bytes)
1836
1836
EEPROM
-
64
64
PDIP16
PSO16
CDIP16W
(See end of Datasheet for Ordering Information)
Rev. 2.4
April 1998
1/68
1
1 page  
ST62T52B ST62T62B/E62B
1.2 PIN DESCRIPTIONS
VDD and VSS. Power is supplied to the MCU via
these two pins. VDD is the power connection and
VSS is the ground connection.
OSCin and OSCout. These pins are internally
connected to the on-chip oscillator circuit. A quartz
crystal, a ceramic resonator or an external clock
signal can be connected between these two pins.
The OSCin pin is the input pin, the OSCout pin is
the output pin.
RESET. The active-low RESET pin is used to re-
start the microcontroller.
TEST/VPP. The TEST must be held at VSS for nor-
mal operation. If TEST pin is connected to a
+12.5V level during the reset phase, the
EPROM/OTP programming Mode is entered.
NMI. The NMI pin provides the capability for asyn-
chronous interruption, by applying an external non
maskable interrupt to the MCU. The NMI input is
falling edge sensitive. It is provided with an on-
chip pullup resistor and Schmitt trigger character-
istics.
PA4-PA5. These 2 lines are organized as one I/O
port (A). Each line may be configured under soft-
ware control as inputs with or without internal pull-
up resistors, interrupt generating inputs with pull-
up resistors, open-drain or push-pull outputs, ana-
log inputs for the A/D converter.
PB0, PB2-PB3, PB6-PB7. These 5 lines are or-
ganized as one I/O port (B). Each line may be con-
figured under software control as inputs with or
without internal pull-up resistors, interrupt gener-
ating inputs with pull-up resistors, open-drain or
push-pull outputs. PB6/ARTIMin and PB7/ARTI-
Mout are either Port B I/O bits or the Input and
Output pins of the ARTimer.
Reset state of PB2-PB3 pins can be defined by
option either with pull-up or high impedance.
PB0, PB2-PB3, PB6-PB7 scan also sink 20mA for
direct LED driving.
PC2-PC3. These 2 lines are organized as one I/O
port (C). Each line may be configured under soft-
ware control as input with or without internal pull-
up resistor, interrupt generating input with pull-up
resistor, analog input for the A/D converter, open-
drain or push-pull output.
Figure 2. ST62T52B, E62B and T62B Pin
Configuration
PB0 1
VPP/TEST 2
PB2 3
PB3 4
ARTIMin/PB6 5
ARTIMout/PB7 6
VDD 7
VSS 8
16 PC2/Ain
15 PC3/Ain
14 NMI
13 RESET
12 OSCout
11 OSCin
10 PA5/Ain
9 PA4/Ain
5/68
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5 Page 
ST62T52B ST62T62B/E62B
MEMORY MAP (Cont’d)
1.3.7 EEPROM Description
EEPROM memory is located in 64-byte pages in
data space. This memory may be used by the user
program for non-volatile data storage.
Data space from 00h to 3Fh is paged as described
in Table 4 . Row Arrangement for Parallel Writing
of EEPROM Locations. EEPROM locations are
accessed directly by addressing these paged sec-
tions of data space.
The EEPROM does not require dedicated instruc-
tions for read or write access. Once selected via the
Data RAM Bank Register, the active EEPROM
page is controlled by the EEPROM Control Regis-
ter (EECTL), which is described below.
Bit E20FF of the EECTL register must be reset prior
to any write or read access to the EEPROM. If no
bank has been selected, or if E2OFF is set, any ac-
cess is meaningless.
Programming must be enabled by setting the
E2ENA bit of the EECTL register.
The E2BUSY bit of the EECTL register is set when
the EEPROM is performing a programming cycle.
Any access to the EEPROM when E2BUSY is set
is meaningless.
Provided E2OFF and E2BUSY are reset, an EEP-
ROM location is read just like any other data loca-
tion, also in terms of access time.
Writing to the EEPROM may be carried out in two
modes: Byte Mode (BMODE) and Parallel Mode
(PMODE). In BMODE, one byte is accessed at a
time, while in PMODE up to 8 bytes in the same
row are programmed simultaneously (with conse-
quent speed and power consumption advantages,
the latter being particularly important in battery
powered circuits).
General Notes:
Data should be written directly to the intended ad-
dress in EEPROM space. There is no buffer mem-
ory between data RAM and the EEPROM space.
When the EEPROM is busy (E2BUSY = “1”)
EECTL cannot be accessed in write mode, it is
only possible to read the status of E2BUSY. This
implies that as long as the EEPROM is busy, it is
not possible to change the status of the EEPROM
Control Register. EECTL bits 4 and 5 are reserved
and must never be set.
Care is required when dealing with the EECTL reg-
ister, as some bits are write only. For this reason,
the EECTL contents must not be altered while ex-
ecuting an interrupt service routine.
If it is impossible to avoid writing to this register
within an interrupt service routine, an image of the
register must be saved in a RAM location, and
each time the program writes to EECTL it must
also write to the image register. The image regis-
ter must be written to first so that, if an interrupt oc-
curs between the two instructions, the EECTL will
not be affected.
Table 4. . Row Arrangement for Parallel Writing of EEPROM Locations
Byte 0 1 2 3 4 5 6
ROW7
ROW6
ROW5
ROW4
ROW3
ROW2
ROW1
ROW0
Dataspace
addresses.
Banks 0 and 1.
7
38h-3Fh
30h-37h
28h-2Fh
20h-27h
18h-1Fh
10h-17h
08h-0Fh
00h-07h
Up to 8 bytes in each row may be programmed simultaneously in Parallel Write mode.
The number of available 64-byte banks (1 or 2) is device dependent.
11/68
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