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STE100P Schematic ( PDF Datasheet ) - ST Microelectronics

Teilenummer STE100P
Beschreibung 10/100 FAST ETHERNET 3.3V TRANSCEIVER
Hersteller ST Microelectronics
Logo ST Microelectronics Logo 




Gesamt 30 Seiten
STE100P Datasheet, Funktion
STE100P
10/100 FAST ETHERNET 3.3V TRANSCEIVER
1 DESCRIPTION
The STE100P, also referred to as STEPHY1, is a
high performance Fast Ethernet physical layer inter-
face for 10Base-T and 100Base-TX applications.
It was designed with advanced CMOS technology to
provide a Media Independent Interface (MII) for easy
attachment to 10/100 Media Access Controllers
(MAC) and a physical media interface for 100Base-
TX of IEEE802.3u and 10Base-T of IEEE802.3.
The STEPHY1 supports both half-duplex and full-du-
plex operation, at 10 and 100 Mbps operation. Its op-
erating mode can be set using auto-negotiation,
parallel detection or manual control. It also allows for
the support of auto-negotiation functions for speed
and duplex detection.
2 FEATURES
2.1 Industry standard
IEEE802.3u 100Base-TX and IEEE802.3
10Base-T compliant
Figure 2. Block Diagram
Figure 1. Package
TQFP64 (10x10x1.40mm)
Table 1. Order Codes
Part Number
STE100P
Package
TQFP64
Support for IEEE802.3x flow control
IEEE802.3u Auto-Negotiation support for
10Base-T and 100Base-TX
MII interface
Standard CSMA/CD or full duplex operation
supported
Industrial temperature compliant
LEDS
LEDS
TX_CLK
TXD[3:0]
TX_ER
TX_EN
MDC
MDIO
100Mb/s
4B/5B
TX Channel
Scrambler
Parallel to
Serial
NRZ To NRZI
Encoder
10Mb/s
NRZ To Manchester
Encoder
Link Pulse
Generator
REGISTERS
Auto
Negotiation
Binary To MLT3
Encoder
10 TX
Filter
Loopback
TRANSMITTER
10/100
TXP
TXN
Clock
Generation
System
Clock
RXD[3:0]
RX_ER
RX_DV
RX_CLK
HW
configuration
pins
HW Config
Power Down
100Mb/s
Descrambler
4B/5B Code Align
RX Channel
Serial to
Parallel
NRZI To NRZ
Decoder
Binary To MLT3
Decoder
Clock Recovery
Adaptive
Equalization
BaseLine
Wander
10Mb/s
NRZ To Manchester
Encoder
Link Pulse
Detector
10 TX Filter
Clock Recovery
SMART
Squelch
RECEIVER
10/100
RXP
RXN
September 2004
Rev. 18
1/31






STE100P Datasheet, Funktion
STE100P
Table 2. Pin Description (continued)
Pin No. Name
Type
Description
5 mf0
4 mf1
3 mf2
2 mf3
1 mf4
I Multi-Function pins. Each mf pin internally drives different configuration
functions. The functions of the five mf inputs are as shown in the table below.
6 fde
Digital Power Pins
39, 45, 62
25, 40, 50
Analog Power Pins
9, 13, 16, 17, 22
7, 10, 14, 20, 24
The logic level of mf0-4 will determine the value that the affected bits will have
upon reset of the STE100P. The operating functions of cfg0, cfg1, and fde
change depending on the state of mf0 (Auto-Negotiation enabled or disabled).
Table 2 shows the relationship between cfg0, cfg1 and fde.
I Full-Duplex Enable.
When A/N is enabled, fde determines full-duplex advertisement capability in
combination with cfg0 and cfg1. (See Table 2)
When A/N is disabled, fde directly affects full-duplex operation and determines
the value of PR0 bit 8 (Full/Half Duplex Mode Select).
When fde is High, full-duplex is enabled and PR0:8 = 1.
When fde is Low, full-duplex is disabled and PR0:8 = 0.
vcce, vcce/i
gnde, gnde/i
vcca
gnda
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6 Page









STE100P pdf, datenblatt
STE100P
Table 5. Register Descriptions (continued)
Bit #
Name
Descriptions
5 LP10H Link Partner’s 10Base-T Half Duplex ability.
0: link partner without 10Base-T ability.
1: link partner with 10Base-T ability.
4~0 LPSF Link partner select field. Default 00001=IEEE 802.3.
PR6- ANE, Auto-Negotiation expansion
15~5
--- Reserved
4 PDF Parallel detection fault.
0: no fault detected.
1: a fault detected via parallel detection function.
3 LPNP Link Partner’s Next Page ability.
0: link partner without next page ability.
1: link partner with next page ability.
2 NP STE100P’s next Page ability.
Always 0, since STE100P without next page ability.
1 PR Page Received.
0: no new page has been received.
1: a new page has been received.
0 LPAN Link Partner Auto-Negotiation ability.
0: link partner has no Auto-Negotiation ability.
1: link partner has Auto-Negotiation ability.
LH = High Latching and cleared by reading.
PR17- XCIIS, XCVR Configuration information and Interrupt Status
15~10
---- Reserved
9 SPEED Configured information of Speed.
0: the speed is 10Mb/s.
1: the speed is 100Mb/s.
8 DUPLEX Configured information of Duplex.
0: the duplex mode is half.
1: the duplex mode is full.
7 PAUSE Configured information of PAUSE function for flow control.
0: PAUSE function is disabled.
1: PAUSE function is enabled
6 ANC Interrupt source of Auto-Negotiation Completed.
0: Auto-Negotiation has not completed yet.
1: Auto-Negotiation has completed.
5 RFD Interrupt source of Remote Fault Detected.
0: there is no remote fault detected.
1: remote fault is detected.
4 LS Interrupt source of Link Fail.
0: link test status is up.
1: link is down.
Default Val RW Type
0 RO
00001
RO
0 RO
0 RO/LH*
0 RO
0 RO
0 RO/LH*
0 RO
0 RO
1 RO
0 RO
0 RO
0 RO/LH*
0 RO/LH*
0 RO/LH*
12/31

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