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PDF ST62E65B Data sheet ( Hoja de datos )
| Número de pieza | ST62E65B | |
| Descripción | (ST6255B / ST6265B) 8-BIT OTP/EPROM MCUs | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ST62E65B (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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ST62T55B
R ST62T65B/E65B
8-BIT OTP/EPROM MCUs WITH A/D CONVERTER,
AUTO-RELOAD TIMER, EEPROM AND SPI
s 3.0 to 6.0V Supply Operating Range
s 8 MHz Maximum Clock Frequency
s -40 to +125°C Operating Temperature Range
s Run, Wait and Stop Modes
s 5 Interrupt Vectors
s Look-up Table capability in Program Memory
s Data Storage in Program Memory:
User selectable size
s Data RAM: 128 bytes
s Data EEPROM: 128 bytes (none on ST62T55B)
s User Programmable Options
s 21 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input
s 8 I/O lines can sink up to 20mA to drive LEDs or
TRIACs directly
s 8-bit Timer/ Counter with 7-bit programmable
prescaler
s 8-bit Auto-reload Timer with 7-bit programmable
prescaler (AR Timer)
s Digital Watchdog
s 8-bit A/D Converter with 13 analog inputs
s 8-bit Synchronous Peripheral Interface (SPI)
s On-chip Clock oscillator can be driven by Quartz
Crystal Ceramic resonator or RC network
s User configurable Power-on Reset
s One external Non-Maskable Interrupt
s ST626x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port)
DEVICE SUMMARY
DEVICE
ST62T55B
ST62T65B
ST62E65B
OTP
(Bytes)
3884
3884
EPROM
(Bytes)
-
-
3884
EEPROM
-
128
128
PDIP28
PSO28
CDIP28W
(See end of Datasheet for Ordering Information)
Rev. 2.4
April 1998
1/74
1
1 page  
ST62T55B ST62T65B/E65B
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST62T55B, ST62T65B and ST62E65B devic-
es are low cost members of the ST62xx 8-bit HC-
MOS family of microcontrollers, which is targeted
at low to medium complexity applications. All
ST62xx devices are based on a building block ap-
proach: a common core is surrounded by a
number of on-chip peripherals.
The ST62E65B is the erasable EPROM version of
the ST62T65B device, which may be used to em-
ulate the ST62T55B and ST62T65B device, as
well as the respective ST6255B and ST6265B
ROM devices.
OTP and EPROM devices are functionally identi-
cal. The ROM based versions offer the same func-
tionality selecting as ROM options the options de-
Fj igure 1. Block Diagram
fined in the programmable option byte of theOTP/
EPROM versions.
OTP devices offer all the advantages of user pro-
grammability at low cost, which make them the
ideal choice in a wide range of applications where
frequent code changes, multiple code versions or
last minute programmability are required.
These compact low-cost devices feature a Timer
comprising an 8-bit counter and a 7-bit program-
mable prescaler, an 8-bit Auto-Reload Timer,
EEPROM data capability (except ST62T55B), a
serial port communication interface, an 8-bit A/D
Converter with 13 analog inputs and a Digital
Watchdog timer, making them well suited for a
wide range of automotive, appliance and industrial
applications.
TEST/VPP
NMI
TEST
8-BIT
A/D CONVERTE R
INTERRUP T
PROGR AM
MEMORY
3884 bytes OTP
(ST62T55B, T6 5B)
3884 bytes EPROM
(ST62E65B)
DATA ROM
USER
SELECTABLE
DATA RAM
128 Bytes
DATA EEPROM
128 Bytes
( ST62T65B/E65B)
PC
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6
8 BIT CORE
POWER
SUPP LY
OSCILLATOR
RESET
PORT A
PORT B
PORT C
AUTORELOAD
TIMER
TIMER
SPI (SERIAL
PE RIPHERAL
INTERFAC E)
DIGITAL
WATCHDOG
PA0..PA7 / Ain
PB0..PB5 / 20 mA Sink
PB6 / ARTimin / 20 mA Sink
PB7 / ARTimout / 20 mA Sink
PC0 / Ain
PC1 / Tim1 / Ain
PC2 / Sin / Ain
PC3 / Sout / Ain
PC4 / Sck / Ain
VDD VSS OSCin OSCout RESET
5/74
5
5 Page 
ST62T55B ST62T65B/E65B
MEMORY MAP (Cont’d)
1.3.6 Data RAM/EEPROM
(DRBR)
Address: E8h — Write only
Bank
Register
70
-
-
-
DRB R
4
-
-
DRBR DRBR
10
Bit 7-5 = These bits are not used
Bit 4 - DRBR4. This bit, when set, selects RAM
Page 2.
Bit 3-2 - Reserved. These bits are not used.
Bit 1 - DRBR1. This bit, when set, selects
EEPROM Page 1.
Bit 0 - DRBR0. This bit, when set, selects
EEPROM Page 0.
The selection of the bank is made by programming
the Data RAM Bank Switch register (DRBR regis-
ter) located at address E8h of the Data Space ac-
cording to Table 1. No more than one bank should
be set at a time.
The DRBR register can be addressed like a RAM
Data Space at the address E8h; nevertheless it is
a write only register that cannot be accessed with
single-bit operations. This register is used to select
the desired 64-byte RAM/EEPROM bank of the
Data Space. The number of banks has to be load-
ed in the DRBR register and the instruction has to
point to the selected location as if it was in bank 0
(from 00h address to 3Fh address).
This register is not cleared during the MCU initiali-
zation, therefore it must be written before the first
access to the Data Space bank region. Refer to
the Data Space description for additional informa-
tion. The DRBR register is not modified when an
interrupt or a subroutine occurs.
Notes :
Care is required when handling the DRBR register
as it is write only. For this reason, it is not allowed
to change the DRBR contents while executing in-
terrupt service routine, as the service routine can-
not save and then restore its previous content. If it
is impossible to avoid the writing of this register in
interrupt service routine, an image of this register
must be saved in a RAM location, and each time
the program writes to DRBR it must write also to
the image register. The image register must be
written first, so if an interrupt occurs between the
two instructions the DRBR is not affected.
In DRBR Register, only 1 bit must be set. Other-
wise two or more pages are enabled in parallel,
producing errors.
Table 3. Data RAM Bank Register Set-up
DRBR
00
01
02
08
10h
other
ST62T55B
None
Not Available
Not Available
Not Available
RAM Page 2
Reserved
ST62T65B/E65B
None
EEPROM Page 0
EEPROM Page 1
Not Available
RAM Page 2
Reserved
11/74
11
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| PDF Descargar | [ Datasheet ST62E65B.PDF ] | |
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