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PDF ST62E62C Data sheet ( Hoja de datos )
| Número de pieza | ST62E62C | |
| Descripción | (ST6252C / ST6262C) 8-BIT OTP/EPROM MCUs | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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ST62T52C
ST62T62C/E62C
8-BIT OTP/EPROM MCUs WITH A/D CONVERTER,
SAFE RESET, AUTO-RELOAD TIMER AND EEPROM
s 3.0 to 6.0V Supply Operating Range
s 8 MHz Maximum Clock Frequency
s -40 to +125°C Operating Temperature Range
s Run, Wait and Stop Modes
s 5 Interrupt Vectors
s Look-up Table capability in Program Memory
s Data Storage in Program Memory:
User selectable size
s Data RAM: 128 bytes
s Data EEPROM: 64 bytes (none on ST62T52C)
s User Programmable Options
s 9 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input
s 5 I/O lines can sink up to 30mA to drive LEDs or
TRIACs directly
s 8-bit Timer/Counter with 7-bit programmable
prescaler
s 8-bit Auto-reload Timer with 7-bit programmable
prescaler (AR Timer)
s Digital Watchdog
s Oscillator Safe Guard
s Low Voltage Detector for Safe Reset
s 8-bit A/D Converter with 4 analog inputs
s On-chip Clock oscillator can be driven by Quartz
Crystal Ceramic resonator or RC network
s User configurable Power-on Reset
s One external Non-Maskable Interrupt
s ST626x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port)
DEVICE SUMMARY
DEVICE
ST62T52C
ST62T62C
ST62E62C
EPROM
(Bytes)
1836
OTP
(Bytes)
1836
1836
EEPROM
-
64
64
February 2002
PDIP16
PSO16
SSOP16
CDIP16W
(See end of Datasheet for Ordering Information)
Rev. 3.0
1/78
1 page  
ST62T52C ST62T62C/E62C
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST62T52C and ST62T62C devices is low cost
members of the ST62xx 8-bit HCMOS family of mi-
crocontrollers, which is targeted at low to medium
complexity applications. All ST62xx devices are
based on a building block approach: a common
core is surrounded by a number of on-chip periph-
erals.
The ST62E62C is the erasable EPROM version of
the ST62T62C device, which may be used to em-
ulate the ST62T52C and ST62T62C devices as
well as the ST6252C and ST6262B ROM devices.
OTP and EPROM devices are functionally identi-
cal. The ROM based versions offer the same func-
tionality selecting as ROM options the options de-
Figure 1. Block Diagram
fined in the programmable option byte of the
OTP/EPROM versions.
OTP devices offer all the advantages of user pro-
grammability at low cost, which make them the
ideal choice in a wide range of applications where
frequent code changes, multiple code versions or
last minute programmability are required.
These compact low-cost devices feature a Timer
comprising an 8-bit counter and a 7-bit program-
mable prescaler, an 8-bit Auto-Reload Timer,
EEPROM data capability (except ST62T52C), an
8-bit A/D Converter with 4 analog inputs and a Dig-
ital Watchdog timer, making them well suited for a
wide range of automotive, appliance and industrial
applications.
TEST/VPP
NMI
TEST
8-BIT
A/D CONVERTER
INTERRUPT
PROGRAM
MEMORY
1836 bytes OTP
(ST62T52C, T62C)
1836 bytes EPROM
(ST62E62C)
DATA ROM
USER
SELECTABLE
DATA RAM
128 Bytes
DATA EEPROM
64 Bytes
(ST62T62C/E62C)
PC
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6
8 BIT CORE
POWER
SUPPLY
OSCILLATOR
RESET
VDD VSS OSCin OSCout RESET
PORT A
PORT B
PORT C
AUTORELOAD
TIMER
TIMER
PA4..PA5 / Ain
PB0, PB2..PB3 / 30 mA Sink
PB6 / ARTimin / 20 mA Sink
PB7 / ARTimout / 20 mA Sink
PC2..PC3 / Ain
DIGITAL
WATCHDOG
5/78
5 Page 
ST62T52C ST62T62C/E62C
MEMORY MAP (Cont’d)
1.3.6 Data RAM/EEPROM
(DRBR)
Address: E8h — Write only
Bank
Register
70
-
-
-
DRBR
4
-
-
-
DRBR
0
Bit 7-5 = These bits are not used
Bit 4 - DRBR4. This bit, when set, selects RAM
Page 2.
Bit 3-1. Not used
Bit 0. DRBR0. This bit, when set, selects EEP-
ROM page 0.
The selection of the bank is made by programming
the Data RAM Bank Switch register (DRBR regis-
ter) located at address E8h of the Data Space ac-
cording to Table 1. No more than one bank should
be set at a time.
The DRBR register can be addressed like a RAM
Data Space at the address E8h; nevertheless it is
a write only register that cannot be accessed with
single-bit operations. This register is used to select
the desired 64-byte RAM bank of the Data Space.
The bank number has to be loaded in the DRBR
register and the instruction has to point to the se-
lected location as if it was in bank 0 (from 00h ad-
dress to 3Fh address).
This register is not cleared during the MCU initiali-
zation, therefore it must be written before the first
access to the Data Space bank region. Refer to
the Data Space description for additional informa-
tion. The DRBR register is not modified when an
interrupt or a subroutine occurs.
Notes :
Care is required when handling the DRBR register
as it is write only. For this reason, it is not allowed
to change the DRBR contents while executing in-
terrupt service routine, as the service routine can-
not save and then restore its previous content. If it
is impossible to avoid the writing of this register in
interrupt service routine, an image of this register
must be saved in a RAM location, and each time
the program writes to DRBR it must write also to
the image register. The image register must be
written first, so if an interrupt occurs between the
two instructions the DRBR is not affected.
In DRBR Register, only 1 bit must be set. Other-
wise two or more pages are enabled in parallel,
producing errors.
Care must also be taken not to change the
E²PROM page (when available) when the parallel
writing mode is set for the E²PROM, as defined in
EECTL register.
Table 3. Data RAM Bank Register Set-up
DRBR
00
01
02
08
10h
other
ST62T52C
None
Not available
Not Available
Not available
RAM Page 2
Reserved
ST62T62C
None
EEPROM page 0
Not Available
Not available
RAM Page 2
Reserved
11/78
11 Page | ||
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| PDF Descargar | [ Datasheet ST62E62C.PDF ] | |
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