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PDF SST34HF1621 Data sheet ( Hoja de datos )
| Número de pieza | SST34HF1621 | |
| Descripción | (SST34HF1621 / SST34HF1641) 16M-bit Concurrent SuperFlash + SRAM Combo Memory | |
| Fabricantes | Silicon Storage Technology | |
| Logotipo |  |
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16 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory
SST34HF1621 / SST34HF1641
SST3 4HF16 21/ 164 116 Mb CSF (x1 6) + 2Mb / 4Mb SRAM (x8/x16 ) MCP Co mboMe morie s
FEATURES:
Data Sheet
• Flash Organization: 1M x16
• Dual-Bank Architecture for Concurrent
Read/Write Operation
– 16 Mbit: 12 Mbit + 4 Mbit
• SRAM Organization:
– 2 Mbit: 256K x8 or 128K x16
– 4 Mbit: 512K x8 or 256K x16
• Single 2.7-3.3V Read and Write Operations
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Current: 25 mA (typical)
– Standby Current: 20 µA (typical)
• Hardware Sector Protection (WP#)
– Protects 4 outer most sectors (4 KWord) in the
larger bank by holding WP# low and unprotects
by holding WP# high
• Hardware Reset Pin (RST#)
– Resets the internal state machine to reading
data array
• Sector-Erase Capability
– Uniform 1 KWord sectors
• Block-Erase Capability
– Uniform 32 KWord blocks
• Read Access Time
– Flash: 70 and 90 ns
– SRAM: 70 and 90 ns
• Latched Address and Data
• Fast Erase and Word-Program:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Word-Program Time: 14 µs (typical)
– Chip Rewrite Time: 8 seconds (typical)
• Automatic Write Timing
– Internal VP P Generation
• End-of-Write Detection
– Toggle Bit
– Data# Polling
– Ready/Busy# pin
• CMOS I/O Compatibility
• JEDEC Standard Command Set
• Conforms to Common Flash Memory Interface
(C FI)
• Packages Available
– 56-ball LFBGA (8mm x 10mm)
PRODUCT DESCRIPTION
The SST34HF1621/1641 ComboMemory devices inte- The SuperFlash technology provides fixed Erase and Pro-
grate a 1M x16 CMOS flash memory bank with a 256K x8/ gram times, independent of the number of Erase/Program
128K x16 or 512K x8/ 256K x16 CMOS SRAM memory cycles that have occurred. Therefore, the system software
bank in a Multi-Chip Package (MCP). These devices are or hardware does not have to be modified or de-rated as is
fabricated using SST’s proprietary, high-performance necessary with alternative flash technologies, whose
CMOS SuperFlash technology incorporating the split-gate Erase and Program times increase with accumulated
cell design and thick oxide tunneling injector to attain better Erase/Program cycles. The SST34HF1621/1641 devices
reliability and manufacturability compared with alternate offer a guaranteed endurance of 10,000 cycles. Data
approaches. The SST34HF1621/1641 devices are ideal for retention is rated at greater than 100 years. With high per-
applications such as cellular phones, GPSs, PDAs and formance Word-Program, the flash memory banks provide
other portable electronic devices in a low power and small a typical Word-Program time of 14 µsec. The entire flash
form factor system.
memory bank can be erased and programmed word-by-
The SST34HF1621/1641 features dual flash memory bank
architecture allowing for concurrent operations between the
two flash memory banks and the SRAM. The devices can
read data from either bank while an Erase or Program
operation is in progress in the opposite bank. The two flash
memory banks are partitioned into 4 Mbit and 12 Mbit with
top or bottom sector protection options for storing boot
code, program code, configuration/parameter data and
www.DataSuserdata.
word in typically 8 seconds for the SST34HF1621/1641,
when using interface features such as Toggle Bit or Data#
Polling to indicate the completion of Program operation. To
protect against inadvertent flash write, the SST34HF1621/
1641 devices contain on-chip hardware and software data
protection schemes.
©200 2 Si lico n Stora ge Te chno log y, Inc.
The SST l ogo a nd Sup erFlash a re regi ste red trade marks of Si lico n Sto rage Te chno logy, Inc.
S711 72-0 5-00 0 2/02
52 3
C oncu rrent Supe rFl ash, CSF, an d Comb oMemo ry are trade marks of Si lico n Sto rage Te chno logy, Inc.
1 Th ese spe cificatio ns are sub ject to ch ang e witho ut n otice.
1 page  
16 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory
SST34HF1621 / SST34HF1641
Data Sheet
Product Identification
SRAM Operation
The Product Identification mode identifies the devices as
the SST34HF1621/1641 and manufacturer as SST. This
mode may be accessed by software operations only. The
hardware device ID Read operation, which is typically used
by programmers cannot be used on this device because of
the shared lines between flash and SRAM in the multi-chip
package. Therefore, application of high voltage to pin A9
may damage this device. Users may use the software
Product Identification operation to identify the part (i.e.,
using the device ID) when using multiple manufacturers in
the same socket. For details, see Tables 3 and 4 for soft-
ware operation, Figure 14 for the software ID entry and
read timing diagram and Figure 23 for the ID entry com-
mand sequence flowchart.
TABLE 1: PR OD U C T I DE N TIFIC A TIO N
Manufacturer’s ID
Device ID
SST34HF1621
SST34HF1641
ADDRESS
0000H
0001H
0001H
DATA
00BFH
2761H
2761H
T1.2 523
Product Identification Mode Exit/
CFI Mode Exit
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read mode.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. Please note that the Software ID Exit/
CFI Exit command is ignored during an internal Program or
Erase operation. See Table 4 for software command
codes, Figure 16 for timing waveform and Figure 23 for a
flowchart.
With BES1# low, BES2 and BEF# high, the
SST34HF162x operates as 256K x8 or 128K x16 CMOS
SRAM, and the SST34HF164x operates as 512K x8 or
256K x16 CMOS SRAM, with fully static operation requir-
ing no external clocks or timing strobes. The CIOs pin
configures the SRAM for x8 or x16 SRAM operation
modes. The SST34HF162x SRAM is mapped into the
first 256 KByte/128 KWord address space of the device,
and the SST34HF164x SRAM is mapped into the first
512 KByte/256 KWord address space. When BES1#,
BEF# are high and BES2 is low, all memory banks are
deselected and the device enters standby. Read and
Write cycle times are equal. The control signals UBS#
and LBS# provide access to the upper data byte and
lower data byte. See Table 3 for SRAM Read and Write
data byte control modes of operation.
SRAM Read
The SRAM Read operation of the SST34HF1621/1641 is
controlled by OE# and BES1#, both have to be low with
WE# and BES2 high for the system to obtain data from the
outputs. BES1# and BES2 are used for SRAM bank selec-
tion. OE# is the output control and is used to gate data from
the output pins. The data bus is in high impedance state
when OE# is high. Refer to the Read cycle timing diagram,
Figure 3, for further details.
SRAM Write
The SRAM Write operation of the SST34HF1621/1641 is
controlled by WE# and BES1#, both have to be low, BES2
have to be high for the system to write to the SRAM. During
the Word-Write operation, the addresses and data are ref-
erenced to the rising edge of either BES1#, WE#, or the
falling edge of BES2 whichever occurs first. The write time
is measured from the last falling edge of BES#1 or WE# or
the rising edge of BES2 to the first rising edge of BES1#, or
WE# or the falling edge of BES2. Refer to the Write cycle
timing diagram, Figures 4 and 5, for further details.
©200 2 Sili con Storag e Te chno log y, Inc.
5
S71 172 -05-0 00 2 /0 2 523
5 Page 
16 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory
SST34HF1621 / SST34HF1641
TABLE 6: SY STEM IN TER FA C E IN FOR M A TION
Address
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
Data
0027H
0036H
0000H
0000H
0004H
0000H
0004H
0006H
0001H
0000H
0001H
0001H
Data
VDD Min (Program/Erase)
DQ7-DQ 4: Volts, DQ3-DQ0: 100 millivolts
VDD Max (Program/Erase)
DQ7-DQ 4: Volts, DQ3-DQ0: 100 millivolts
VPP Min (00H = no V P P pin)
VPP Max (00H = no VPP pin)
Typical time out for Word-Program 2N µs (24 = 16 µs)
Typical time out for Min size buffer program 2N µs (00H = not suppor ted)
Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms)
Typical time out for Chip-Erase 2N ms (26 = 64 ms)
Maximum time out for Word-Program 2 N times typical (21 x 24 = 32 µs)
Maximum time out for buffer program 2N times typical
Maximum time out for individual Sector/Block-Erase 2 N times typical
(21 x 24 = 32 ms)
Maximum time out for Chip-Erase 2N times typical (21 x 26 = 128 ms)
TABLE 7: DEVI C E GEO ME TR Y IN FOR M ATI ON
Address
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
Data
0015H
0001H
0000H
0000H
0000H
0002H
00FFH
0003H
0008H
0000H
001FH
0000H
0000H
0001H
Data
Device size = 2N Byte (15H = 21; 221 = 2M Bytes)
Flash Device Interface description; 0001H = x16-only asynchronous interface
Maximum number of byte in multi-byte wr ite = 2N (00H = not suppor ted)
Number of Erase Sector/Block sizes suppor ted by device
Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
y = 1023 + 1 = 1024 sectors (03FF = 1023)
z = 8 x 256 Bytes = 2 KByte/sector (0008H = 8)
Block Information (y + 1 = Number of blocks; z x 256B = block size)
y = 31 + 1 = 32 blocks (001F = 31)
z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)
Data Sheet
T6.0 523
T7.0 523
©200 2 Sili con Storag e Te chno log y, Inc.
11
S71 172 -05-0 00 2 /0 2 523
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SST34HF1621.PDF ] | |
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