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PDF SST34HF1681 Data sheet ( Hoja de datos )
| Número de pieza | SST34HF1681 | |
| Descripción | (SST34HF1621A / SST34HF1641A / SST34HF1681) 16M-bit Concurrent SuperFlash + SRAM Combo Memory | |
| Fabricantes | Silicon Storage Technology | |
| Logotipo |  |
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16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1621A / SST34HF1641A / SST34HF1681
SST34HF168116Mb CSF (x16) + 2/4/8 Mb SRAM (x16) MCP ComboMemory
FEATURES:
Data Sheet
• Flash Organization: 1M x16
• Dual-Bank Architecture for Concurrent
Read/Write Operation
– 16 Mbit: 12 Mbit + 4 Mbit
• SRAM Organization:
– 2 Mbit: 128K x16
– 4 Mbit: 256K x16
– 8 Mbit: 512K x16
• Single 2.7-3.3V Read and Write Operations
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Current: 25 mA (typical)
– Standby Current: 20 µA (typical)
• Hardware Sector Protection (WP#)
– Protects 4 outer most sectors (4 KWord) in the
larger bank by holding WP# low and unprotects
by holding WP# high
• Hardware Reset Pin (RST#)
– Resets the internal state machine to reading
data array
• Sector-Erase Capability
– Uniform 1 KWord sectors
• Block-Erase Capability
– Uniform 32 KWord blocks
• Read Access Time
– Flash: 70 and 80 ns
– SRAM: 70 and 80 ns
• Latched Address and Data
• Fast Erase and Word-Program:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Word-Program Time: 14 µs (typical)
– Chip Rewrite Time: 8 seconds (typical)
• Automatic Write Timing
– Internal VPP Generation
• End-of-Write Detection
– Toggle Bit
– Data# Polling
– Ready/Busy# pin
• CMOS I/O Compatibility
• JEDEC Standard Command Set
• Conforms to Common Flash Memory Interface
(CFI)
• Packages Available
– 56-ball LFBGA (8mm x 10mm)
– 62-ball LFBGA (8mm x 10mm)
PRODUCT DESCRIPTION
The SST34HF16x1A and SST34HF1681 ComboMemory
devices integrate a 1M x16 CMOS flash memory bank with
either a 128K x16, 256K x16, or 512K x16 CMOS SRAM
memory bank in a multi-chip package (MCP). These devices
are fabricated using SST’s proprietary, high-performance
CMOS SuperFlash technology incorporating the split-gate
cell design and thick oxide tunneling injector to attain better
reliability and manufacturability compared with alternate
approaches. The SST34HF16x1A and SST34HF1681
devices are ideal for applications such as cellular phones,
GPS devices, PDAs, and other portable electronic devices in
a low power and small form factor system.
The SST34HF16x1A and SST34HF1681 feature dual
flash memory bank architecture allowing for concurrent
operations between the two flash memory banks and the
SRAM. The devices can read data from either bank while
an Erase or Program operation is in progress in the oppo-
site bank. The two flash memory banks are partitioned into
4 Mbit and 12 Mbit with bottom sector protection options for
storing boot code, program code, configuration/parameter
data and user data.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore, the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles. The SST34HF16x1A and SST34HF1681
devices offer a guaranteed endurance of 10,000 cycles.
Data retention is rated at greater than 100 years. With high
performance Word-Program, the flash memory banks pro-
vide a typical Word-Program time of 14 µsec. The entire
flash memory bank can be erased and programmed word-
by-word in typically 8 seconds for the SST34HF16x1A and
SST34HF1681, when using interface features such as Tog-
gle Bit or Data# Polling to indicate the completion of Pro-
gram operation. To protect against inadvertent flash write,
the SST34HF16x1A and SST34HF1681 devices contain
on-chip hardware and software data protection schemes.
©2003 Silicon Storage Technology, Inc.
S71217-02-000
7/03
1
www.DataSheet4U.com
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. Intel is a registered trademark of Intel Corporation.
CSF and ComboMemory are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
1 page  
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1621A / SST34HF1641A / SST34HF1681
Data Sheet
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the
device to read array data. When the RST# pin is held low
for at least TRP, any in-progress operation will terminate and
return to Read mode (see Figure 19). When no internal
Program/Erase operation is in progress, a minimum period
of TRHR is required after RST# is driven high before a valid
Read can take place (see Figure 18).
The Erase operation that has been interrupted needs to be
reinitiated after the device resumes normal operation mode
to ensure data integrity. See Figures 18 and 19 for timing
diagrams.
Software Data Protection (SDP)
The SST34HF16x1A and SST34HF1681 provide the
JEDEC standard Software Data Protection scheme for all
data alteration operations, i.e., Program and Erase. Any
Program operation requires the inclusion of the three-byte
sequence. The three-byte load sequence is used to initiate
the Program operation, providing optimal protection from
inadvertent Write operations, e.g., during the system
power-up or power-down. Any Erase operation requires the
inclusion of six-byte sequence. The SST34HF16x1A and
SST34HF1681 are shipped with the Software Data Protec-
tion permanently enabled. See Table 4 for the specific soft-
ware command codes. During SDP command sequence,
invalid commands will abort the device to Read mode
within TRC. The contents of DQ15-DQ8 are “Don’t Care”
during any SDP command sequence.
age to pin A9 may damage this device. Users may use the
software Product Identification operation to identify the part
(i.e., using the device ID) when using multiple manufactur-
ers in the same socket. For details, see Tables 3 and 4 for
software operation, Figure 15 for the Software ID Entry and
Read timing diagram and Figure 24 for the ID Entry com-
mand sequence flowchart.
TABLE 1: PRODUCT IDENTIFICATION
Manufacturer’s ID
Device ID
SST34HF1621A/1641A/1681
ADDRESS
0000H
0001H
DATA
00BFH
2761H
T1.0 1217
Product Identification Mode Exit/
CFI Mode Exit
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read mode.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. Please note that the Software ID Exit/
CFI Exit command is ignored during an internal Program or
Erase operation. See Table 4 for software command
codes, Figure 17 for timing waveform and Figure 24 for a
flowchart.
Common Flash Memory Interface (CFI)
The SST34HF16x1A and SST34HF1681 also contain the
CFI information to describe the characteristics of the device.
In order to enter the CFI Query mode, the system must
write three-byte sequence, same as Software ID Entry com-
mand with 98H (CFI Query command) to address 555H in
the last byte sequence. Once the device enters the CFI
Query mode, the system can read CFI data at the
addresses given in Tables 5 through 7. The system must
write the CFI Exit command to return to Read mode from
the CFI Query mode.
Product Identification
The Product Identification mode identifies the device as the
SST34HF16x1A or SST34HF1681 and manufacturer as
SST. This mode may be accessed by software operations
only. The hardware device ID Read operation, which is typ-
ically used by programmers cannot be used on this device
because of the shared lines between flash and SRAM in
the multi-chip package. Therefore, application of high volt-
SRAM Operation
With BES1# low, BES2 and BEF# high, the
SST34HF16x1A and SST34HF1681 operate as either
128K x16, 256K x16, or 512K x16 CMOS SRAM, with
fully static operation requiring no external clocks or timing
strobes. The SST34HF16x1A and SST34HF1681 SRAM
is mapped into the first 512 KWord address space. When
BES1#, BEF# are high and BES2 is low, all memory
banks are deselected and the device enters standby.
Read and Write cycle times are equal. The control sig-
nals UBS# and LBS# provide access to the upper data
byte and lower data byte. See Table 3 for SRAM Read
and Write data byte control modes of operation.
©2003 Silicon Storage Technology, Inc.
5
S71217-02-000
7/03
5 Page 
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1621A / SST34HF1641A / SST34HF1681
Data Sheet
TABLE 4: SOFTWARE COMMAND SEQUENCE
Command
Sequence
Word-Program
Sector-Erase
Block-Erase
Chip-Erase
Software ID Entry5
CFI Query Entry5
Software ID Exit/
CFI Exit6
1st Bus
Write Cycle
Addr1 Data2
5555H AAH
5555H AAH
5555H AAH
5555H AAH
5555H AAH
5555H AAH
5555H AAH
2nd Bus
Write Cycle
Addr1 Data2
2AAAH 55H
2AAAH 55H
2AAAH 55H
2AAAH 55H
2AAAH 55H
2AAAH 55H
2AAAH 55H
3rd Bus
Write Cycle
Addr1 Data2
5555H A0H
5555H 80H
5555H 80H
5555H 80H
5555H 90H
5555H 98H
5555H F0H
4th Bus
Write Cycle
Addr1 Data2
WA3 Data
5555H AAH
5555H AAH
5555H AAH
5th Bus
Write Cycle
Addr1 Data2
2AAAH
2AAAH
2AAAH
55H
55H
55H
1. Address format A14-A0 (Hex),Address A19-A15 can be VIL or VIH, but no other value, for the Command sequence.
2. Data format DQ15-DQ8 can be VIL or VIH, but no other value, for Command sequence.
3. WA = Program Word address
4. SAX for Sector-Erase; uses A19-A11 address lines
BAX, for Block-Erase; uses A19-A15 address lines
5. The device does not remain in Software Product Identification Mode if powered down.
6. With A20-A1 = 0; SST Manufacturer’s ID = 00BFH, is read with A0=0
SST34HF16x1A/1681 Device ID = 2761H, is read with A0=1.
6th Bus
Write Cycle
Addr1 Data2
SAX4
BAX4
5555H
30H
50H
10H
T4.1 1217
TABLE 5: CFI QUERY IDENTIFICATION STRING1
Address
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
Data
0051H
0052H
0059H
0001H
0007H
0000H
0000H
0000H
0000H
0000H
0000H
Data
Query Unique ASCII string “QRY”
Primary OEM command set
Address for Primary Extended Table
Alternate OEM command set (00H = none exists)
Address for Alternate OEM extended Table (00H = none exits)
1. Refer to CFI publication 100 for more details.
T5.0 1217
©2003 Silicon Storage Technology, Inc.
11
S71217-02-000
7/03
11 Page | ||
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| PDF Descargar | [ Datasheet SST34HF1681.PDF ] | |
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