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STA015 Schematic ( PDF Datasheet ) - ST Microelectronics

Teilenummer STA015
Beschreibung (STA015x) MPEG 2.5 LAYER III AUDIO DECODER WITH ADPCM CAPABILITY
Hersteller ST Microelectronics
Logo ST Microelectronics Logo 




Gesamt 30 Seiten
STA015 Datasheet, Funktion
STA015
STA015B STA015T
MPEG 2.5 LAYER III AUDIO DECODER
WITH ADPCM CAPABILITY
SINGLE CHIP MPEG2 LAYER 3 DECODER
SUPPORTING:
– All features specified for Layer III in ISO/IEC
11172-3 (MPEG 1 Audio)
– All features specified for Layer III in ISO/IEC
13818-3.2 (MPEG 2 Audio)
m– Lower sampling frequencies syntax exten-
osion, (not specified by ISO) called MPEG 2.5
.cDECODES LAYER III STEREO CHANNELS,
DUAL CHANNEL, SINGLE CHANNEL (MONO)
SUPPORTING ALL THE MPEG 1 & 2
USAMPLING FREQUENCIES AND THE
EXTENSION TO MPEG 2.5:
t448, 44.1, 32, 24, 22.05, 16, 12, 11. 025, 8 KHz
ACCEPTS MPEG 2.5 LAYER III
eELEMENTARY COMPRESSED BITSTREAM
WITH DATA RATE FROM 8 Kbit/s UP TO 320
eKbit/s
hADPCM CODEC CAPABILITIES:
– sample frequency from 8 kHz to 32 kHz
S– sample size from 8 bits to 32 bits
– encoding algorithm: DVI,
taITU-G726 pack (G723-24, G721,G723-40)
– Tone control and fast-forward capability
aEASY PROGRAMMABLE GPSO INTERFACE
FOR ENCODED DATA UP TO 5Mbit/s
.D(TQFP44 & LFBGA 64)
DIGITAL VOLUME CONTROL
DIGITAL BASS & TREBLE CONTROL
wBYPASS MODE FOR EXTERNAL AUDIO
SOURCE
wSERIAL BITSTREAM INPUT INTERFACE
wEASY PROGRAMMABLE ADC INPUT
SO28
TQFP44
LFBGA64
ORDERING NUMBER: STA015$ (SO28)
STA015T$ (TQFP44)
STA015B$ (LFBGA 8x8)
INDICATORS
I2C CONTROL BUS
LOW POWER 2.4V CMOS TECHNOLOGY
WIDE RANGE OF EXTERNAL CRYSTALS
FREQUENCIES SUPPORTED
APPLICATIONS
PC SOUND CARDS
MULTIMEDIA PLAYERS
VOICE RECORDERS
DESCRIPTION
The STA015 is a fully integrated high flexibility
MPEG Layer III Audio Decoder, capable of decod-
ing Layer III compressed elementary streams, as
specified in MPEG 1 and MPEG 2 ISO standards.
The device decodes also elementary streams
compressed by using low sampling rates, as spec-
INTERFACE
ANCILLARY DATA EXTRACTION VIA I2C
INTERFACE.
SERIAL PCM OUTPUT INTERFACE (I2S AND
OTHER FORMATS)
PLL FOR INTERNAL CLOCK AND FOR
OUTPUT PCM CLOCK GENERATION
CRC CHECK AND SYNCHRONISATION
ERROR DETECTION WITH SOFTWARE
March 2004
ified by MPEG 2.5. STA015 receives the input
mdata through a Serial input Interface. The decoded
osignal is a stereo, mono, or dual channel digital
.coutput that can be sent directly to a D/A converter,
Uby the PCM Output Interface.
t4This interface is software programmable to adapt
ethe STA015 digital output to the most common
eDACs architectures used on the market. The func-
htional STA015 chip partitioning is described in
SFig.1a and Fig.1b.
www.Data 1/55






STA015 Datasheet, Funktion
STA015 STA015B STA015T
ELECTRICAL CHARACTERISTICS: VDD = 3.3V ±0.3V; Tamb = 0 to 70°C; Rg = 50unless otherwise
specified
DC OPERATING CONDITIONS
Symbol
Parameter
Value
VDD Power Supply Voltage
2.4 to 3.6V
Tj Operating Junction Temperature
-20 to 125°C
GENERAL INTERFACE ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Condition
Min. Typ. Max. Unit Note
IIL Low Level Input Current
Without pull-up device
Vi = 0V
-10
10 µA
1
IIH High Level Input Current
Without pull-up device
Vi = VDD
-10
10 µA
1
Vesd Electrostatic Protection
Leakage < 1µA
2000
V2
Notes: 1. The leakage currents are generally very small, < 1nA. The value given here is a maximum that can occur after an electrostatic
stress on the pin.
2. Human Body Model.
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Condition
Min. Typ. Max. Unit Note
VIL Low Level Input Voltage
0.2*VDD V
VIH High Level Input Voltage
0.8*VDD
V
Vol Low Level Output Voltage
Iol = Xma
0.4V
V 1, 2
Voh High Level Output Voltage
0.85*VDD
V 1, 2
Notes: 1. Takes into account 200mV voltage drop in both supply lines.
2. X is the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability.
Symbol
Parameter
Test Condition
Ipu Pull-up current
Vi = 0V; pin numbers 7, 24
and 26;
Rpu Equivalent Pull-up Resistance
Notes: 1. Min. condition: VDD = 2.7V, 125°C Min process
Max. condition: VDD = 3.6V, -20°C Max.
Min.
-25
Typ.
-66
50
Max.
-125
Unit Note
µA 1
k
POWER DISSIPATION
Symbol
Parameter
PD Power Dissipation
@ VDD = 2.4V
Test Condition
Sampling_freq 24 kHz
Sampling_freq 32 kHz
Sampling_freq 48 kHz
Min. Typ Max Unit Note
76 mW
79 mW
85 mW
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6 Page









STA015 pdf, datenblatt
STA015 STA015B STA015T
3.4 ADC Inteface
Beside the serial input interface based on SDI and SCKR lines a 3 wire flexible and user configurable input
interface is also available, suitable to interface with most A/D converters. To configure this interface 4 spe-
cific I2C registers are available (ADC_ENABLE, ADC_CONF, ADC_WLEN and ADC_WPOS). Refer to
registers description for more details.
3.5 General Purpose I/O Interface
A new general purpose I/O interface has been added to this device (TQFP44 and LFBGA64 only). Actually
only the strobe line is used in ADPCM encoding mode to provide an interrupt; other pins are reserved for
future use. The related configuration register is GPIO_CONF. See the following summary for related pin
usage:
Name
Description
Dir
I/ODATA [0]
..................
I/ODATA [7]
GPIO data line
I/O
.....
I/O
GPIO_STROBE
GPIO strobe line
I/O
4.0 ADPCM ENCODING: OVERVIEW
According to the previously described interfaces there are 4 ways to manage ADPCM data stream while
encoding. Input interface can be either the serial receiver block (SDI + SCKR + DATA_REQ lines) or the
ADC specific interface.
Output interfaces can be either the I2C bus (with or without interrupt line) or the GPSO high-speed serial
interface (GPSO_REQ + GPSO_ DATA + GPSO_SCKR lines). This result in the following 4 methods to
handle encoding flow:
INPUT (data to encode)
Output (encoded data)
Available on package
ADC I/F (SDI_ADC + LRCK_ADC + SCK_ADC) GPSO I/F (GPSO_REQ + GPSO_DATA + TQFP44/LFBGA64
GPSO_SCKR)
ADC I/F (SDI_ADC + LRCK_ADC + SCK_ADC) I2C + Interrupt (SCL + SDA +DATA_REQ)
SO28/TQFP44
LFBGA64
SERIAL I/F (SCKR + SDI + DATA_REQ)
GPSO I/F (GPSO_REQ + GPSO_DATA + TQFP44/LFBGA64
GPSO_SCKR)
SERIAL I/F (SCKR + SDI + DATA_REQ) (*)
I2C (polling) (SCL + SDA)
SO28/TQFP44
LFBGA64
(*) STA013 Compatible mode
Figure 10.
STA015
GPSO_SCKR
GPSO_DATA
GPSO_REQ
MCU
GPSO_SCKR
GPSO_REQ
GPSO_DATA
D00AU1145
12/55

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