PDF MT48LC8M16LFF4 Data sheet ( Hoja de datos )

Número de pieza	MT48LC8M16LFF4
Descripción	(MT48xxxMxxLFFx) SYNCHRONOUS DRAM
Fabricantes	Micron Technology
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No Preview Available ! 128Mb: x16, x32 MOBILE SDRAM SYNCHRONOUS DRAM MT48G8M16LFFF, MT48G8M16LFF4, MT48LC8M16LFFF, MT48LC8M16LFF4, MT48V8M16LFF4, MT48V8M16LFFF MT48LC4M32LFFC, MT48LC4M32LFF5, MT48V4M32LFFC, MT48V4M32LFF5 For the latest data sheet, please refer to the Micron Web site: www.micron.com/dramds Features • Temperature Compensated Self Refresh (TCSR) Figure 1: Pin Assignment (Top View) • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can mbe changed every clock cycle • Internal banks for hiding row access/precharge o• Programmable burst lengths: 1, 2, 4, 8, or full page .c• Auto Precharge, includes CONCURRENT auto precharge, and Auto Refresh Modes • Self Refresh Mode; standard and low power U• 64ms, 4,096-cycle refresh • LVTTL-compatible inputs and outputs t4• Low voltage power supply • Partial Array Self Refresh power-saving mode eOPTIONS MARKING e• VDD/VDDQ 3.3V/3.3V h3.0V/3.0V1 2.5V/2.5V – 1.8V S• Configurations ta8 Meg x 16 (2 Meg x 16 x 4 banks) LC G V 8M16 4 Meg x 32 (1 Meg x 32 x 4 banks) • Package/Ball out a54-ball FBGA (8mm x 9mm)2 54-ball FBGA (8mm x 9mm)2 Lead-Free .D54-ball VFBGA (8mm x 8mm)2 54-ball VFBGA (8mm x 8mm)2 Lead-Free 90-ball FBGA (11mm x 13mm)3 w90-ball FBGA (11mm x 13mm)3 Lead-Free 90-ball VFBGA (8mm x 13mm)3 w90-ball VFBGA (8mm x 13mm)3 Lead-Free • Timing (Cycle Time) w m8ns @ CL = 3 (125 MHz) .co10ns @ CL = 3 (100 MHz) 4M32 FF BF F4 B4 FC BC F5 B5 -8 -10 • Temperature UCommercial (0°C to +70°C) t4Industrial (-40°C to +85°C) None IT eExtended (-25°C to +75°C) XT heNOTE: S1. Check with factory for configuration and availability. ta2. x16 Only. .Da3. x32 Only. 54-Ball FBGA 123456789 A VSS DQ15 VSSQ VDDQ DQ0 VDD B DQ14 DQ13 VDDQ VSSQ DQ2 DQ1 C DQ12 DQ11 VSSQ VDDQ DQ4 DQ3 D DQ10 DQ9 VDDQ VSSQ DQ6 DQ5 E DQ8 NC VSS VDD LDQM DQ7 F UDQM CLK CKE CAS# RAS# WE# G NC/A12 A11 A9 BA0 BA1 CS# H A8 A7 A6 A0 A1 A10 J VSS A5 A4 Top View (Ball Down) A3 A2 VDD 8 Meg x 16 4 Meg x 32 Configuration 2 Meg x 16 x 4 banks 1 Meg x 32 x 4 banks Refresh Count 4K 4K Row Addressing 4K (A0–A11) 4K (A0–A11) Bank Addressing 4 (BA0, BA1) 4 (BA0, BA1) Column Addressing 512 (A0–A8) 256 (A0–A7) Part Number Example: MT48V8M16LFFF-8 Table 1: Key Timing Parameters SPEED CLOCK GRADE FREQUENCY -8 125 MHz -10 100 MHz -8 100 MHz -10 83 MHz -8 50 MHz -10 40 MHz ACCESS TIME CL=1* CL=2* CL=3* – – 7ns – – 7ns – 8ns – – 8ns – 19ns 22ns – – – – tRCD 20ns 20ns 20ns 20ns 20ns 20ns tRP 20ns 20ns 20ns 20ns 20ns 20ns *CL = CAS (READ) latency w09005aef8071a76b wwMobileY95W_3V_1.fm - Rev. H 10/03 EN 1 ©2001 Micron Technology, Inc. All rights reserved. 1 page 128Mb: x16, x32 MOBILE SDRAM Figure 2: 90-Ball FBGA Pin Assignment (Top View) 123456789 A DQ26 DQ24 VSS B DQ28 VDDQ VSSQ C VSSQ DQ27 DQ25 D VSSQ DQ29 DQ30 E VDDQ DQ31 NC F VSS DQM3 A3 G A4 A5 A6 H A7 A8 NC J CLK CKE A9 K DQM1 NC NC L VDDQ DQ8 VSS M VSSQ DQ10 DQ9 N VSSQ DQ12 DQ14 P DQ11 VDDQ VSSQ R DQ13 DQ15 VSS VDD DQ23 DQ21 VDDQ VSSQ DQ19 DQ22 DQ20 VDDQ DQ17 DQ18 VDDQ NC DQ16 VSSQ A2 DQM2 VDD A10 A0 A1 NC BA1 A11 BA0 CS# RAS# CAS# WE# DQM0 VDD DQ7 VSSQ DQ6 DQ5 VDDQ DQ1 DQ3 VDDQ VDDQ VSSQ DQ4 VDD DQ0 DQ2 Ball and Array 09005aef8071a76b MobileY95W_3V_2.fm - Rev. H 10/03 EN 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. 5 Page Functional Description In general, the 128Mb SDRAMs (2 Meg x16 x 4 banks and 1 Meg x 32 x 4 banks) are quad-bank DRAMs that operate at 3.3V or 2.5V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16’s 33,554,432- bit banks is organized as 4,096 rows by 512 columns by 16 bits. Each of the x32’s 33,554,432-bit banks is orga- nized as 4,096 rows by 256 columns by 32bits. Read and write accesses to the SDRAM are burst ori- ented; accesses start at a selected location and con- tinue for a programmed number of locations in a programmed sequence. Accesses begin with the regis- tration of an ACTIVE command, which is then fol- lowed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A0-A11 select the row). The address bits (x16: A0-A8; x32: A0-A7) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the SDRAM must be ini- tialized. The following sections provide detailed infor- mation covering device initialization, register definition, command descriptions and device opera- tion. Initialization SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined opera- tion. Once power is applied to Vdd and VddQ (simulta- neously) and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the SDRAM requires a 100µs delay prior to issuing any command other than a COM- MAND INHIBIT or NOP. Starting at some point during this 100µs period and continuing at least through the end of this period, Command Inhibit or NOP com- mands should be applied. Once the 100µs delay has been satisfied with at least one Command Inhibit or NOP command having been applied, a PRECHARGE command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state. Once in the idle state, two AUTO refresh cycles must be performed. After the AUTO refresh cycles are com- plete, the SDRAM is ready for mode register program- ming. Because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. 128Mb: x16, x32 MOBILE SDRAM Register Definition Mode Register In order to achieve low power consumption, there are two mode registers in the Mobile component, Mode Register and Extended Mode Register. For this section, Mode Register is referred to. Extended Mode register is discussed on 14. The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in Figure 5. The mode reg- ister is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. Mode Register bits M0-M2 specify the burst length, M3 specifies the type of burst (sequential or inter- leaved), M4-M6 specify the CAS latency, M7 and M8 specify the operating mode, M9, M10, and M11 should be set to zero. M12 and M13 should be set to zero to prevent extended mode register. The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Vio- lating either of these requirements will result in unspecified operation. Burst Length Read and write accesses to the SDRAM are burst ori- ented, with the burst length being programmable, as shown in Figure 5. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A8 (x16) or A1-A7 (x32) when the burst length is set to two; by A2-A8 (x16) or A2-A7 (x32) when the burst length is set to four; and by A3-A8 (x16) or A3- A7 (x32) when the burst length is set to eight. The 09005aef8071a76b MobileY95W_3V_2.fm - Rev. H 10/03 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. 11 Page

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