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PDF MB81F641642C Data sheet ( Hoja de datos )

Número de pieza MB81F641642C
Descripción 4 x 1 M x 16 BIT SYNCHRONOUS DYNAMIC RAM
Fabricantes Fujitsu 
Logotipo Fujitsu Logotipo



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FUJITSU SEMICONDUCTOR
DATA SHEET
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DS05-11045-1E
MEMORY
CMOS
4 × 1 M × 16 BIT
SYNCHRONOUS DYNAMIC RAM
MB81F641642C-102/-103/-102L/-103L
CMOS 4-Bank × 1,048,576-Word × 16 Bit
Synchronous Dynamic Random Access Memory
s DESCRIPTION
The Fujitsu MB81F641642C is a CMOS Synchronous Dynamic Random Access Memory (SDRAM) containing
67,108,864 memory cells accessible in a 16-bit format. The MB81F641642C features a fully synchronous
operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which
enables high performance and simple user interface coexistence. The MB81F641642C SDRAM is designed to
reduce the complexity of using a standard dynamic RAM (DRAM) which requires many control signal timing
constraints, and may improve data bandwidth of memory as much as 5 times more than a standard DRAM.
The MB81F641642C is ideally suited for workstations, personal computers, laser printers, high resolution graphic
adapters/accelerators and other applications where an extremely large memory and bandwidth are required and
where a simple interface is needed.
s PRODUCT LINE & FEATURES
Parameter
CL - tRCD - tRP
Clock Frequency
Burst Mode Cycle Time
Access Time From Clock (CL = 3)
Operating Current (2 banks active)
Power Down Mode Current (ICC2P)
Self Refresh Current (ICC6)
MB81F641642C
-102
-102L
-103
-103L
2 - 2 - 2 clk min.
3 - 2 - 2 clk min.
100 MHz max.
100 MHz max.
10 ns min.
10 ns min.
6 ns max.
6 ns max.
105 mA max.
105 mA max.
2 mA max. 1 mA max. 2 mA max. 1 mA max.
1 mA max. 500 µA max. 1 mA max. 500 µA max.
• Single +3.3 V Supply ±0.3 V tolerance
• LVTTL compatible I/O
• 4 K refresh cycles every 65.6 ms
• Four bank operation
• Burst read/write operation and burst
read/single write operation capability
• Standard and low power versions
• Programmable burst type, burst length, and
CAS latency
• Auto-and Self-refresh (every 16 µs)
• CKE power down mode
• Output Enable and Input Data Mask

1 page




MB81F641642C pdf
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MB81F641642C-102/-103/-102L/-103L
s FUNCTIONAL TRUTH TABLE Note 1
COMMAND TRUTH TABLE Notes 2, 3, and 4
Function
CKE
Notes Symbol
n-1 n
Device Deselect
No Operation
Burst Stop
Read
Read with Auto-precharge
Write
*5 DESL
*5 NOP
BST
*6 READ
*6 READA
*6 WRIT
H
H
H
H
H
H
X
X
X
X
X
X
Write with Auto-precharge
Bank Active (RAS)
Precharge Single Bank
Precharge All Banks
Mode Register Set
*6 WRITA
*7 ACTV
PRE
PALL
*8, 9 MRS
H
H
H
H
H
X
X
X
X
X
CS
RAS CAS
WE
A13,
A12
(BA)
A10
(AP)
A11
A9 to
A0
HX XXX X X X
LH HHX X X X
LHHLX X X X
LH LHV L X V
LH LHV H X V
LH LLV L X V
LH LLVHX V
L L HHV V V V
LL HLV L X X
LL HLXHX X
LL LLXXXV
Notes: *1.
*2.
*3.
*4.
*5.
*6.
*7.
*8.
*9.
V = Valid, L = Logic Low, H = Logic High, X = either L or H.
All commands assumes no CSUS command on previous rising edge of clock.
All commands are assumed to be valid state transitions.
All inputs are latched on the rising edge of clock.
NOP and DESL commands have the same effect on the part.
READ, READA, WRIT and WRITA commands should only be issued after the corresponding bank has
been activated (ACTV command). Refer to STATE DIAGRAM.
ACTV command should only be issued after corresponding bank has been precharged (PRE or PALL
command).
Required after power up.
MRS command should only be issued after all banks have been precharged (PRE or PALL command).
Refer to STATE DIAGRAM.
5

5 Page





MB81F641642C arduino
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MB81F641642C-102/-103/-102L/-103L
(Continued)
Current
State
Refreshing
CS RAS CAS WE
HXXX
L HH X
LHLX
Addr
X
X
X
L LHX
X
Mode
Register
Setting
LLLX
HXXX
L HHH
L HH L
LHLX
X
X
X
X
X
L L XX
X
ABBREVIATIONS:
RA = Row Address
CA = Column Address
BA = Bank Address
AP = Auto Precharge
Command
Function
DESL
NOP (Idle after tRC)
NOP/BST NOP (Idle after tRC)
READ/READA/
WRIT/WRITA
Illegal
ACTV/
PRE/PALL
Illegal
REF/SELF/
MRS
Illegal
DESL
NOP (Idle after tRSC)
NOP
NOP (Idle after tRSC)
BST Illegal
READ/READA/
WRIT/WRITA
Illegal
ACTV/PRE/
PALL/REF/
SELF/MRS
Illegal
Notes
11

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