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Teilenummer | 28F128W18 |
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Beschreibung | (28FxxxW18) 1.8 V Wireless Flash Memory | |
Hersteller | Intel | |
Logo | ||
Gesamt 70 Seiten 1.8 Volt Intel® Wireless Flash Memory
(W18)
28F320W18, 28F640W18, 28F128W18
Preliminary Datasheet
Product Features
s Performance
— 70 ns Asynchronous reads for 32 and 64 Mbit,
90 ns for 128 Mbit
m— 14 ns Clock to Data Output (tCHQV)
— 20 ns Page Mode Read Speed
o— 4-Word, 8-Word, and Continuous-Word Burst
Modes
.c— Burst and Page Modes in Parameter and Main
Partitions
— Programmable WAIT Configuration
— Enhanced Factory Programming Mode@
U3.50 µs/Word (Typ)
— Glueless 12 V interface for Fast Factory
t4Programming @ 8 µs/Word (Typ)
— 1.8 V Low-Power Programming @ 12 µs/Word
(Typ)
e— Program or Erase during Reads
s Architecture
e— Multiple 4-Mbit Partitions
— Dual-Operation: Read-While-Write or Read-
hWhile-Erase
— Eight, 4-Kword Parameter Code and Data
Blocks
S— 32-Kword Main Code and Data Blocks
— Top and Bottom Parameter Configurations
tas Power Operation
— 1.7 V to 1.95 V Read and Write Operations
— 1.7 V to 2.24 V VCCQ for I/O Isolation
a— Standby Current: 5 µA (Typ)
— Read Current: 7 mA (Typ)
s Software
— 5 µs (Typ) Program Suspend
— 5 µs (Typ) Erase Suspend
— Intel® Flash Data Integrator (FDI) Software
Optimized
— Intel Basic Command Set Compatible
— Common Flash Interface (CFI)
s Quality and Reliability
— Extended Temperature: –40 °C to +85 °C
— Minimum 100,000 Erase Cycles per Block
— ETOX™ VII Flash Technology (0.18 µm)
s Security
— 128-bit Protection Register: 64 Unique Device
Identifier Bits; 64 User-Programmable OTP
Bits
— Absolute Write Protection ⇒VPP = GND
— Erase/Program Lockout during Power
Transitions
— Individual Dynamic Zero-Latency Block
Locking
— Individual Block Lock-Down
s Density and Packaging
— 32 Mbit and 128 Mbit in a VF BGA Package
— 64 Mbit in a µBGA*Package
— 56 Active Ball Matrix, 0.75 mm Ball-Pitch
µBGA* and VF BGA Packages
— 16-bit wide Data Bus
.DThe 1.8 Volt Intel® Wireless Flash memory with flexible multi-partition dual-operation provides high-
performance asynchronous and synchronous burst reads. It is an ideal memory for low-voltage burst CPUs.
wCombining high read performance with flash memory’s intrinsic non-volatility, 1.8 Volt Intel Wireless Flash
memory eliminates the traditional system-performance paradigm of shadowing redundant code memory from
slow nonvolatile storage to faster execution memory. It reduces the total memory requirement that increases
wreliability and reduces overall system power consumption and cost.
mThe 1.8 Volt Intel Wireless Flash memory’s flexible multi-partition architecture allows programming or erasing to
woccur in one partition while reading from another partition. This allows for higher data write throughput
ocompared to single partition architectures. The dual-operation architecture also allows two processors to
.cinterleave code operations while program and erase operations take place in the background. The designer can
also choose the size of the code and data partitions via the flexible multi-partition architecture.
t4UThe 1.8 Volt Intel Wireless Flash memory is manufactured on Intel’s 0.18 µm ETOX™ VII process technology. It
is available in µBGA and VF BGA packages which are ideal for board-constrained applications.
SheeNotice: This document contains preliminary information on new products in production. The
taspecifications are subject to change without notice. Verify with your local Intel sales office that
you have the latest datasheet before finalizing a design.
.Da 290701-003
www June 2001
6 Page 1.8 Volt Intel® Wireless Flash Memory (W18)
2.3 Memory Partitioning
The 1.8 Volt Intel® Wireless Flash memory is divided into 4-Mbit physical partitions which allows
simultaneous RWW or RWE operations and allows users to segment code and data areas on 4-Mbit
boundaries. The device’s asymmetrically-blocked architecture enables system code and data
integration within a single flash device. Each block can be erased independently in block erase
mode. Simultaneous program and erase is not allowed. Only one partition at a time can be actively
programming or erasing. See Table 2, “Bottom Parameter Memory Map” on page 7 and Table 3,
“Top Parameter Memory Map” on page 8.
The 32-Mbit device has eight partitions, the 64-Mbit device has 16 partitions, and the 128-Mbit
device has 32 partitions. Each device density contains one parameter partition and several main
partitions: the 4-Mbit parameter partition contains eight 4-Kword parameter blocks and seven 32-
Kword main blocks; and each 4-Mbit main partition contains eight 32-Kword blocks each.
The bulk of the array is divided into main blocks that can store code or data, and parameter blocks
allow storage of frequently updated small parameters that would normally be stored in EEPROM.
By using software techniques, the word-rewrite functionality of EEPROMs can be emulated.
.
6 Preliminary
12 Page | ||
Seiten | Gesamt 70 Seiten | |
PDF Download | [ 28F128W18 Schematic.PDF ] |
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