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CD1865 Schematic ( PDF Datasheet ) - Intel Corporation

Teilenummer CD1865
Beschreibung Intelligent Eight-channel Communications Controller
Hersteller Intel Corporation
Logo Intel Corporation Logo 




Gesamt 30 Seiten
CD1865 Datasheet, Funktion
CD1865
Intelligent Eight-Channel Communications Controller
Datasheet
Product Features
s Eight full-duplex asynchronous channels s Software compatibility with the CD180 and
supporting data rates up to 115.2 kbps
Note: To support this data rate, the
specified system clock frequency is
mrequired.
os Register-based interrupt acknowledges
eliminate need for separate interrupt
.cacknowledge signals
s Automatic prioritizing scheme allows
device to respond to an interrupt
Uacknowledge with the highest internal
interrupt pending (host-programmable)
t4s Sophisticated interrupt schemes
— Vectored interrupts
e—Fair Share interrupts
— Good Datainterrupts for improved
ethroughput
h—Simultaneous interrupt requests for three
classes of interrupts: Rx, Tx, and
Smodem state changes
s Independent baud-rate generators for each
tachannel/direction
CD1864 devices
s Generation and detection of special
characters
s Automatic flow control
— In-band (Xon, Xoff generation, and
detection)
— Out-of-band (DTR/DSR or RTS/CTS)
s On-chip FIFO — 8 bytes each for Rx, Tx,
and Status
s Line break detection and generation
s Multiple-chip daisy-chain cascading
feature
s Odd, even, forced, or no parity
s modem/general-purpose I/O signals per
channel
s System clock up to 66 MHz (x2), 33MHz
(x1)
s CMOS technology in 100-pin MQFP
www.Da .DataSheet4U.comAs of May 18, 2001, this document replaces the Basis
wwwCommunications Corp. document CL-CD1865 — Intelligent 8-Channel Communications Controller. May 2001






CD1865 Datasheet, Funktion
CD1865 Intelligent Eight-Channel Communications Controller
11.0
12.0
Index
10.5.2 Unclocked Bus Interface ...................................................................... 136
Package Specifications ....................................................................................... 145
Ordering Information ............................................................................................ 146
....................................................................................................................................... 147
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
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17
18
19
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21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Functional Block Diagram ..................................................................................... 9
Internal Block Diagram........................................................................................ 22
Foreground/Background Internal Structure......................................................... 24
Internal Operation Flow Chart ............................................................................. 25
Internal Service Acknowledge Decision Tree...................................................... 30
Internal Fair-Share Operation ............................................................................. 31
Receive Timer Operation .................................................................................... 34
Three-Level Interrupt with Three-Level Acknowledge Example.......................... 38
Three-Level Interrupt with Single-Level Acknowledge Example ......................... 39
Single-Level Interrupt with Single-Level Acknowledge Example ........................ 40
Simple Software Polled Interface Example ......................................................... 41
Polled Code Sequence ....................................................................................... 42
Interrupt Code Sequence .................................................................................... 43
Internal Block Diagram........................................................................................ 46
2¥ Clock Option................................................................................................... 47
............................................................................................................................ 48
Typical Unclocked Bus Interface......................................................................... 53
Typical Clocked Bus Interface............................................................................. 54
Incorrect VME Interface ...................................................................................... 56
Correct VME Interface......................................................................................... 57
Bit Synchronization in CD1865 ........................................................................... 58
Receive Operation .............................................................................................. 59
No New Data Timer Logic ................................................................................... 67
Transmitter Operation ......................................................................................... 69
Receiver Flow-Control Logic ............................................................................... 73
Transmitter Flow-Control Logic ........................................................................... 76
Local and Remote Loopback Logic..................................................................... 82
Initialization ......................................................................................................... 85
Clocked Bus Interface Reset............................................................................. 130
Clocked Bus Interface Clocks ........................................................................... 131
Clocked Bus Interface Read Cycle,
Motorola-Style Handshake ............................................................................... 131
Clocked Bus Interface Service Acknowledgment Cycle,
Motorola-Style Handshake ............................................................................... 132
Clocked Bus Interface Write Cycle,
Motorola-Style Handshake ............................................................................... 133
Clocked Bus Interface Read Cycle,
Intel-Style Handshake ...................................................................................... 134
Clocked Bus Interface Service Acknowledgment Cycle,
Intel-Style Handshake ...................................................................................... 135
Clocked Bus Interface Write Cycle, Intel-Style Handshake.............................. 136
6 Datasheet

6 Page









CD1865 pdf, datenblatt
CD1865 Intelligent Eight-Channel Communications Controller
Note: To support 115.2 kbps, a system clock of 66 MHz is required. System design is simplified in the
CD1865 by providing a choice of crystal or external clock operation, at 1×- or 2×-rated frequency.
12 Datasheet

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