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PDF LM628N-6 Data sheet ( Hoja de datos )
| Número de pieza | LM628N-6 | |
| Descripción | Precision Motion Controller | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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November 1999
LM628/LM629
Precision Motion Controller
General Description
The LM628/LM629 are dedicated motion-control processors
designed for use with a variety of DC and brushless DC
servo motors, and other servomechanisms which provide a
quadrature incremental position feedback signal. The parts
perform the intensive, real-time computational tasks required
for high performance digital motion control. The host control
software interface is facilitated by a high-level command set.
The LM628 has an 8-bit output which can drive either an
8-bit or a 12-bit DAC. The components required to build a
servo system are reduced to the DC motor/actuator, an in-
cremental encoder, a DAC, a power amplifier, and the
LM628. An LM629-based system is similar, except that it
provides an 8-bit PWM output for directly driving H-switches.
The parts are fabricated in NMOS and packaged in a 28-pin
dual in-line package or a 24-pin surface mount package
(LM629 only). Both 6 MHz and 8 MHz maximum frequency
versions are available with the suffixes -6 and -8, respec-
tively, used to designate the versions. They incorporate an
SDA core processor and cells designed by SDA.
Features
n 32-bit position, velocity, and acceleration registers
n Programmable digital PID filter with 16-bit coefficients
n Programmable derivative sampling interval
n 8- or 12-bit DAC output data (LM628)
n 8-bit sign-magnitude PWM output data (LM629)
n Internal trapezoidal velocity profile generator
n Velocity, target position, and filter parameters may be
changed during motion
n Position and velocity modes of operation
n Real-time programmable host interrupts
n 8-bit parallel asynchronous host interface
n Quadrature incremental encoder interface with index
pulse input
n Available in a 28-pin dual in-line package or a 24-pin
surface mount package (LM629 only)
FIGURE 1. Block Diagram
DS009219-1
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS009219
www.national.com
1 page  
AC Electrical Characteristics (Continued)
DS009219-4
FIGURE 2. Quadrature Encoder Input Timing
FIGURE 3. Clock and Reset Timing
DS009219-5
FIGURE 4. Status Byte Read Timing
DS009219-6
5 www.national.com
5 Page 
Theory of Operation (Continued)
LM628 READING AND WRITING OPERATIONS
The host processor writes commands to the LM628 via the
host I/O port when Port Select (PS ) input (Pin 16) is logic
low. The desired command code is applied to the parallel
port line and the Write (WR ) input (Pin 15) is strobed. The
command byte is latched into the LM628 on the rising edge
of the WR input. When writing command bytes it is neces-
sary to first read the status byte and check the state of a flag
called the “busy bit” (Bit 0). If the busy bit is logic high, no
command write may take place. The busy bit is never high
longer than 100 µs, and typically falls within 15 µs to 25 µs.
The host processor reads the LM628 status byte in a similar
manner: by strobing the Read (RD ) input (Pin 13) when PS
(Pin 16) is low; status information remains valid as long as
RD is low.
Writing and reading data to/from the LM628 (as opposed to
writing commands and reading status) are done with PS (Pin
16) logic high. These writes and reads are always an integral
number (from one to seven) of two-byte words, with the first
byte of each word being the more significant. Each byte re-
quires a write (WR ) or read (RD ) strobe. When transferring
data words (byte-pairs), it is necessary to first read the status
byte and check the state of the busy bit. When the busy bit is
logic low, the user may then sequentially transfer both bytes
comprising a data word, but the busy bit must again be
checked and found to be low before attempting to transfer
the next byte pair (when transferring multiple words). Data
transfers are accomplished via LM628-internal interrupts
(which are not nested); the busy bit informs the host proces-
sor when the LM628 may not be interrupted for data transfer
(or a command byte). If a command is written when the busy
bit is high, the command will be ignored.
The busy bit goes high immediately after writing a command
byte, or reading or writing a second byte of data (See Figure
5 thru Figure 7).
MOTOR OUTPUTS
The LM628 DAC output port can be configured to provide ei-
ther a latched eight-bit parallel output or a multiplexed 12-bit
output. The 8-bit output can be directly connected to a
flow-through (non-input-latching) D/A converter; the 12-bit
output can be easily demultiplexed using an external 6-bit
latch and an input-latching 12-bit D/A converter. The DAC
output data is offset-binary coded; the 8-bit code for zero is
80 hex and the 12-bit code for zero is 800 hex. Values less
than these cause a negative torque to be applied to the mo-
tor and, conversely, larger values cause positive motor
torque. The LM628, when configured for 12-bit output, pro-
vides signals which control the demultiplexing process. See
for details.
The LM629 provides 8-bit, sign and magnitude PWM output
signals for directly driving switch-mode motor-drive amplifi-
ers. Figure 11 shows the format of the PWM magnitude out-
put signal.
DS009219-13
FIGURE 11. PWM Output Signal Format (Sign output (pin 18) not shown)
Command
RESET
PORT8
PORT12
DFH
SIP
LPEI
LPES
SBPA
SBPR
Type
Initialize
Initialize
Initialize
Initialize
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
TABLE 2. LM628 User Command Set
Description
Hex
Reset LM628
Select 8-Bit Output
Select 12-Bit Output
Define Home
Set Index Position
Interrupt on Error
Stop on Error
Set Breakpoint, Absolute
Set Breakpoint, Relative
00
05
06
02
03
1B
1A
20
21
11
Data
Bytes
0
0
0
0
0
2
2
4
4
Note
1
2
2
1
1
1
1
1
1
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| PDF Descargar | [ Datasheet LM628N-6.PDF ] | |
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