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NQ80220 Schematic ( PDF Datasheet ) - LSI Logic Corporation

Teilenummer NQ80220
Beschreibung (NQ80220 / NQ80221) Ethernet Media Interface Adapter
Hersteller LSI Logic Corporation
Logo LSI Logic Corporation Logo 




Gesamt 30 Seiten
NQ80220 Datasheet, Funktion
et4U.com 100BASE-MTeXd/1ia08BIn0AteS2rEf2a8-c00Te2/E82A0t0hd/8ea20rp22nt2ee11rt98184
taSheFeatures
s Single Chip 100Base-TX / 10Base-T Physical Layer
aSolution
.Ds Dual Speed - 100/10 Mbps
wws Half And Full Duplex
w s MII Interface To Ethernet Controller
ms MI Interface For Configuration & Status
os Optional Repeater Interface
.cs AutoNegotiation: 10/100, Full/Half Duplex
s Meets All Applicable IEEE 802.3, 10Base-T,
100Base-TX Standards
Us On Chip Wave Shaping - No External Filters
t4Required
s Adaptive Equalizer
es Baseline Wander Correction
es Interface to External 100Base-T4 PHY
s LED Outputs
h- Link
- Activity
S- Collision
- Full Duplex
ta- 10/100
- User Programmable
as Many User Features And Options
s Few External Components
.Ds Pin configuration
- 44L PLCC - 80220
www .com- 64L LQFP - 80221
Note: Check for latest Data Sheet revision
before starting any designs.
SEEQ Data Sheets are now on the Web, at
www.lsilogic.com.
This document is an LSI Logic document. Any
reference to SEEQ Technology should be
considered LSI Logic.
Description
The 80220/80221 are highly integrated analog interface
IC's for twisted pair Ethernet applications. The 80220/
80221 can be configured for either 100 Mbps (100Base-
TX) or 10 Mbps (10Base-T) Ethernet operation. The
80220 is packaged in a 44L package, while the 80221 is
packaged in a 64L package and contains a few more
features.
The 80220/80221 consist of 4B5B/Manchester encoder/
decoder, scrambler/descrambler, 100Base-TX/10Base-T
twisted pair transmitter with wave shaping and output
driver, 100Base-TX/10Base-T twisted pair receiver with
on chip equalizer and baseline wander correction, clock
and data recovery, AutoNegotiation, controller interface
(MII), and serial port (MI).
The addition of internal output waveshaping circuitry and
on-chip filters eliminates the need for external filters nor-
mally required in 100Base-TX and 10Base-T applications.
The 80220/80221 can automatically configure itself for
100 or 10 Mbps and Full or Half Duplex operation with the
on-chip AutoNegotiation algorithm.
The 80220/80221 can access eleven 16-bit registers though
the Management Interface (MI) serial port. These registers
contain configuration inputs, status outputs, and device
capabilities.
The 80220/80221 are ideal as media interfaces for
100Base-TX/10Base-T adapter cards, motherboards, re-
peaters, switching hubs, and external PHY's.
www.DataSheet4U4-11
MD400159/E






NQ80220 Datasheet, Funktion
80220/80221
Pin Description continued
Pin# Pin
44L 64L Name
I/O Description
18 18 RX_ER / O Receive Error Output. This controller interface output is asserted active high when a
RXD4
coding or other specified errors are detected on the receive twisted pair inputs and it is
clocked out on falling edges of RX_CLK.
If the device is placed in the Bypass 4B5B Decoder mode, this pin is reconfigured to be the
fifth RXD receive data output, RXD4.
15 12 COL
O Collision Output. This controller interface output is asserted active high when a collision
between transmit and receive data is detected.
13 10 MDC
I Management Interface (MI) Clock Input. This MI clock shifts serial data into and out of
MDIO on rising edges.
14 11 MDIO
I/O Management Interface (MI) Data Input/Output. This bidirectional pin contains serial MI
data that is clocked in and out on rising edges of the MDC clock.
12 9 MDINT I/O Management Interface Interrupt Output/Management Interface Address Input. This
(MDA4) O.D. pin is an interrupt output and is asserted active low whenever there is a change in certain
Pullup MI serial port register bits, and deasserted after all changed bits have been read
out.
During powerup or reset, this pin is high impedance and the value on this pin is latched
in as the physical device address MDA4 for the MI serial port
8 4 PLED3 I/O Programmable LED Output/Management Interface Address Input. The default func-
(MDA3) O.D. tion of this pin is to be a 100 Mbps Link Detect output. This pin can also be programmed
Pullup through the MI serial port to indicate other events or be user controlled. This pin can drive
an LED from VCC.
When programmed as 100 Mbps Link Detect Output (default):
1= No Detect
0 = 100 Mbps Link Detected
During powerup or reset, this pin is high impedance and the value on this pin is latched in
as the physical device address MDA3 for the MI serial port.
7 3 PLED2 I/O Programmable LED Output/Management Interface Address Input. The default func-
(MDA2) O.D. tion of this pin is to be an Activity Detect output. This pin can also be programmed through
Pullup the MI serial port to indicte other events or be user controlled. This pin can drive an LED
from VCC.
When programmed as an Activity Detect Output (default):
1 = No Activity
0 = Transmit Or Receive Packet Occurred, Hold Low for 100 mS
During powerup or reset, this pin is high impedance and the value on this pin is latched in
as the physical device address MDA2 for the MI serial port.
6 62 PLED1 I/O Programmable LED Output/Management Interface Address Input. The default func-
(MDA1) Pullup tion of this pin is to be a Full Duplex Detect output. This pin can also be programmed
through the MI serial port to indicate other events or be user controlled. This pin can drive
an LED from both VCC and GND.
When programmed as Full Duplex Detect Output (default).
1 = Half Duplex
0 = Full Duplex
During powerup or reset, this pin is high impedance and the value on this pin is latched in
as the physical address device address MDA1 for the MI serial port.
MD400159/E
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NQ80220 pdf, datenblatt
80220/80221
On the receive side for 100 Mbps operation, the twisted
pair receiver receives incoming encoded and scrambled
MLT-3 data from the twisted pair cable, remove any high
frequency noise, equalizes the input signal to compensate
for the effects of the cable, qualifies the data with a squelch
algorithm, and converts the data from MLT-3 coded twisted
pair levels to internal digital levels. The output of the
twisted pair receiver then goes to a clock and data recov-
ery block which recovers a clock from the incoming data,
uses the clock to latch in valid data into the device, and
converts the data back to NRZ format. The NRZ data is
then unscrambled and decoded by the 4B5B decoder and
descrambler, respectively, and outputted to an external
Ethernet controller by the controller interface.
10 Mbps operation is similar to the 100 Mbps operation
except, (1) there is no scrambler/descrambler, (2) the
encoder/decoder is Manchester instead of 4B5B, (3) the
data rate is 10 Mbps instead of 100 Mbps, and (4) the
twisted pair symbol data is two level Manchester instead
of ternary MLT-3.
The AutoNegotiation block automatically configures the
device for either 100Base-TX or 10Base-T, and for either
Full or Half Duplex. This configuration is based on the
capabilities selected for this device and the capabilities
detected from a remote device.
The Management Interface, (hereafter referred to as the
MI serial port), is a two pin bidirectional link through which
configuration inputs can be set and status outputs can be
read.
Each block plus the operating modes are described in
more detail in the following sections. Since the 80220/
80221 can operate either as a 100Base-TX or a 10Base-T
device, each of the following sections describes the perfor-
mance of the respective section in both the 100 and 10
Mbps modes.
3.2 DIFFERENCES BETWEEN 80220 AND 80221
The differences between the 80220 and 80221 are sum-
marized in Table 1. For more information on each of these
features, refer to the appropriate sections where these
features are described.
Table 1. 80220 vs. 80221
Feature
80220
80221
Package
44L PLCC
64L LQFP
# LED Outputs
4
6
External
100Base-T4
Interface
No
Yes
Repeater Mode
Pin
No
Yes
3.3 CONTROLLER INTERFACE
3.3.1 General
The 80220/80221 has two interfaces to an external con-
troller: Media Independent Interface (referred to as the
MII) and Five Bit interface (referred to as the FBI).
3.3.2 MII - 100 Mbps
The MII is a nibble wide packet data interface defined in
IEEE 802.3 and shown in Figure 3. The 80220/80221
meets all the MII requirements outlined in IEEE 802.3. The
80220/80221 can directly connect, without any external
logic, to any Ethernet controllers or other devices which
also complies with the IEEE 802.3 MII specifications. The
MII frame format is shown in Figure 3.
The MII consists of eighteen signals: four transmit data
bits (TXD[3:0]), transmit clock (TX_CLK), transmit enable
(TX_EN), transmit error (TX_ER), four receive data bits
(RXD[3:0]), receive clock (RX_CLK), carrier sense (CRS),
receive data valid (RX_DV), receive data error (RX_ER),
and collision (COL). The transmit and receive clocks
operate at 25 MHz in 100 Mbps mode.
On the transmit side, the TX_CLK output runs continu-
ously at 25 Mhz. When no data is to be transmitted, TX_EN
has to be deasserted. While TX_EN is deasserted, TX_ER
and TXD[3:0] are ignored and no data is clocked into the
device. When TX_EN is asserted on the rising edge of
TX_CLK, data on TXD[3:0] is clocked into the device on
rising edges of the TX_CLK output clock. TXD[3:0] input
data is nibble wide packet data whose format needs to be
the same as specified in IEEE 802.3 and shown in Figure
3. When all data on TXD[3:0] has been latched into the
device, TX_EN has to be deasserted on the rising edge of
TX_CLK.
TX_ER is also clocked in on rising edges of the TX_CLK
clock. TX_ER is a transmit error signal which, when
asserted, will substitute an error nibble in place of the
normal data nibble that was clocked in on TXD[3:0]. The
error nibble is defined to be the /H/ symbol which is defined
in IEEE 802.3 and shown in Table 2.
Since OSCIN input clock generates the TX_CLK output
clock, TXD[3:0], TX_EN, and TX_ER are also clocked in
on rising edges of OSCIN.
On the receive side, as long as a valid data packet is not
detected, CRS and RX_DV are deasserted and RXD[3:0]
is held low. When the start of packet is detected , CRS and
RX_DV are asserted on falling edge of RX_CLK. The
assertion of RX_DV indicates that valid data is clocked out
on RXD[3:0] on falling edges of the RX_CLK clock. The
RXD[3:0] data has the same frame structure as the TXD[3:0]
data and is specified in IEEE 802.3 and shown in Figure 3.
MD400159/E
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