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PDF CY7C139AV Data sheet ( Hoja de datos )
| Número de pieza | CY7C139AV | |
| Descripción | (CY7C006AV - CY7C145AV) Dual Port Static RAM | |
| Fabricantes | Cypress Semiconductor | |
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CY7C138AV CY7C139AV CY7C144AV CY7C145AV CY7C006AV CY7C016AV CY7C007AV CY7C017AV 3.3V 4K/8K/16K/32K x 8/9
Dual-Port Static RAM
CY7C138AV/144AV/006AV
Sheet4U.com 3.C3YV7D4CKu1a/3C8l9-YKPA7/Vo1C/r610tK40S57/t3AAa2VVtiKc//00R11x76A8AAM/VV9Features
ta• True Dual-Ported memory cells which allow
asimultaneous access of the same memory location
.D• 4K/8K/16K/32K x 8 organizations
(CY7C0138AV/144AV/006AV/007AV)
w• 4K/8K/16K/32K x 9 organizations
w(CY7C0139AV/145AV/016AV/017AV)
w • 0.35-micron CMOS for optimum speed/power
• High-speed access: 20/25 ns
m• Low operating power
o— Active: ICC = 115 mA (typical)
.c— Standby: ISB3 = 10 µA (typical)
ULogic Block Diagram
t4R/WL
CEL
eOEL
he[1]
taSI/O0L–I/O7/8L
8/9
I/O
Control
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 16/18 bits or more using Master/
Slave chip select when using more than one device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flag for port-to-port communication
• Pin select for Master or Slave
• Commercial and Industrial Temperature Ranges
• Available in 68-pin PLCC (all) and 64-pin TQFP
(7C006AV & 7C144AV)
I/O
Control
R/WR
CER
OER
8/9 [1]
I/O0R–I/O7/8R
a[2]
.DA0L–A11–14L
12–15
Address
Decode
True Dual-Ported
RAM Array
Address
Decode
12–15
w[2]
A0L–A11–14L
wCEL
mOEL
w oR/WL
.cSEML [3]
UBUSYL
t4INTL
12–15
Interrupt
Semaphore
Arbitration
eeM/S
hFor the most recent information, visit the Cypress web site at www.cypress.com
SNotes:
ta1. I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices.
2. A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices; A0–A14 for 32K devices;
a3. BUSY is an output in master mode and an input in slave mode.
12–15
[2]
A0R–A11–14R
[2]
A0R–A11–14R
CER
OER
R/WR
[3] SEMR
BUSYR
INTR
ww.DCypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
wDocument #: 38-06051 Rev. *B
Revised June 23, 2004
1 page  
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Pin Definitions
Left Port Right Port
Description
CEL
R/WL
OEL
A0L–A14L
I/O0L–I/O8L
SEML
INTL
BUSYL
M/S
CER
R/WR
OER
A0R–A14R
I/O0R–I/O8R
SEMR
INTR
BUSYR
Chip Enable
Read/Write Enable
Output Enable
Address (A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices; A0–A14 for 32K)
Data Bus Input/Output (I/O0–I/O7 for x8 devices and I/O0–I/O8 for x9)
Semaphore Enable
Interrupt Flag
Busy Flag
Master or Slave Select
VCC
GND
Power
Ground
NC No Connect
Architecture
The CY7C138AV/144AV/006AV/007AV and CY7C139AV/
145AV/016AV/017AV consist of an array of 4K, 8K, 16K, and 32K
words of 8 and 9 bits each of dual-port RAM cells, I/O and address
lines, and control signals (CE, OE, R/W). These control pins permit
independent access for reads or writes to any location in memory. To
handle simultaneous writes/reads to the same location, a BUSY pin
is provided on each port. Two interrupt (INT) pins can be utilized for
port-to-port communication. Two semaphore (SEM) control pins are
used for allocating shared resources. With the M/S pin, the device
can function as a master (BUSY pins are outputs) or as a slave
(BUSY pins are inputs). The device also has an automatic power-
down feature controlled by CE. Each port is provided with its own
output enable control (OE), which allows data to be read from the
device.
Functional Description
The CY7C138AV/144AV/006AV/007AV and CY7C139AV/
145AV/ 016AV/017AV are low-power CMOS 4K, 8K, 16K, and
32K x8/9 dual-port static RAMs. Various arbitration schemes
are included on the devices to handle situations when multiple
processors access the same piece of data. Two ports are pro-
vided, permitting independent, asynchronous access for reads
and writes to any location in memory. The devices can be uti-
lized as standalone 8/9-bit dual-port static RAMs or multiple
devices can be combined in order to function as a 16/18-bit or
wider master/slave dual-port static RAM. An M/S pin is provid-
ed for implementing 16/18-bit or wider memory applications
without the need for separate master and slave devices or
additional discrete logic. Application areas include interpro-
cessor/multiprocessor designs, communications status buffer-
ing, and dual-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE),
Read or Write Enable (R/W), and Output Enable (OE). Two
flags are provided on each port (BUSY and INT). BUSY sig-
nals that the port is trying to access the same location currently
being accessed by the other port. The Interrupt flag (INT) per-
mits communication between ports or systems by means of a
mail box. The semaphores are used to pass a flag, or token,
from one port to the other to indicate that a shared resource is
in use. The semaphore logic is comprised of eight shared
latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared re-
source is in use. An automatic power-down feature is con-
trolled independently on each port by a Chip Select (CE) pin.
Read and Write Operations
When writing data must be set up for a duration of tSD before
the rising edge of R/W in order to guarantee a valid write. A write
operation is controlled by either the R/W pin (see Write Cycle No. 1
waveform) or the CE pin (see Write Cycle No. 2 waveform). Required
inputs for non-contention operations are summarized in Table 1.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must occur before the data is read on the output; other-
wise the data read is not deterministic. Data will be valid on the
port tDDD after the data is presented on the other port.
When reading the device, the user must assert both the OE
and CE pins. Data will be available tACE after CE or tDOE after OE is
asserted. If the user wishes to access a semaphore flag, then the
SEM pin must be asserted instead of the CE pin and OE must also
be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (FFF for the
CY7C138AV/9AV, 1FFF for the CY7C144AV/5AV, 3FFF for the
CY7C006AV/16AV, 7FFF for the CY7C007AV/17AV) is the
mailbox for the right port and the second-highest memory lo-
cation (FFE for the CY7C138AV/9AV, 1FFE for the
CY7C144AV/5AV, 3FFE for the CY7C006AV/16AV, 7FFE for
the CY7C007AV/17AV) is the mailbox for the left port. When
one port writes to the other port’s mailbox, an interrupt is gen-
erated to the owner. The interrupt is reset when the owner
reads the contents of the mailbox. The message is user de-
fined.
Document #: 38-06051 Rev. *B
Page 5 of 20
5 Page 
Switching Waveforms (continued)
Write Cycle No. 1: R/W Controlled Timing[30, 31, 32, 33]
ADDRESS
tWC
OE
CE [35]
R/W
DATA OUT
DATA IN
tSA
[36]
tAW
tPWE[33]
tHZWE[34]
tSD
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
tHZOE[34]
tHA
tLZWE
tHD
[36]
Write Cycle No. 2: CE Controlled Timing[30, 31, 32, 37]
ADDRESS
tWC
CE [35]
R/W
tSA
tAW
tSCE
DATA IN
tSD
tHA
tHD
Notes:
30. R/W must be HIGH during all address transitions.
31. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM.
32. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
33. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be
as short as the specified tPWE.
34. Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
35. To access RAM, CE = VIL, SEM = VIH.
36. During this period, the I/O pins are in the output state, and input signals must not be applied.
37. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
Document #: 38-06051 Rev. *B
Page 11 of 20
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| PDF Descargar | [ Datasheet CY7C139AV.PDF ] | |
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