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Número de pieza | AS7C34096A | |
Descripción | 3.3V 512K X8 CMOS SRAM | |
Fabricantes | Alliance Semiconductor Corporation | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de AS7C34096A (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
No Preview Available ! February 2004
AS7C34096A
.com ®
t4U 3.3V 512K × 8 CMOS SRAM
eeFeatures
h• Pin compatible to AS7C34096
S• Industrial and commercial temperature
ta• Organization: 524,288 words × 8 bits
a• Center power and ground pins
.D• High speed
w- 10/12/15/20 ns address access time
w- 4/5/6/7 ns output enable access time
w• Low power consumption: ACTIVE
- 650 mW / max @ 10 ns
m• Low power consumption: STANDBY
o- 18 mW / max CMOS
.cLogic block diagram
UVCC
t4GND
eeAA01
A2
A3
hA4
A5
A6
SA7
A8
ww.Data mA9
Input buffer
524,288 × 8
Array
(4,194,304)
Column decoder
Control
Circuit
I/O1
I/O8
WE
OE
CE
• Equal access and cycle times
• Easy memory expansion with CE, OE inputs
• TTL-compatible, three-state I/O
• JEDEC standard packages
- 400 mil 36-pin SOJ
- 44-pin TSOP 2
- 48 pin BGA. 6 X 9mm
• ESD protection ≥ 2000 volts
P• iLnatacrhr-uapngcuermreennt t≥s200 mA
36-pin SOJ (400 mil)
A0
A1
A2
A3
A4
CE
I/O1
IG/VONC2DC
I/O3
I/O4
WE
A5
A6
A7
A8
A9
1 36
2 35
3 34
4 33
5 32
6 31
7 30
8 29
9 28
10 27
11 26
12 25
13 24
14 23
15 22
16 21
17 20
18 19
NC
A18
A17
A16
A15
OE
I/O8
I/O7
GVI/ONCC6D
I/O5
A14
A13
A12
A11
A10
NC
44-pin TSOP 2
NC
NC
A0
A1
A2
A3
A4
CE
I/O1
IG/VONC2DC
1
2
3
54
6
7
89
10
11
12
44
43
42
4401
39
38
3376
35
34
33
I/O3 13 32
I/WOA4E5
A6
14 31
15 30
1167 2298
A7
A8
18 27
19 26
AN9C
20
21
25
24
NC 22 23
NC
NC
AN1C8
A17
A16
A15
IO/OE8
I/O7
GVI/OCNC6D
AI/O145
A13
A12
A11
NAC10
NC
NC
48-pin BGA Package
123456
A A0 A1 NC A3 A6 A8
B I/O5 A2 WE A4
A7 I/O1
C I/O6 NC NC A5 NC I/O2
D VSS NC NC NC NC VCC
E VCC NC NC NC NC VSS
F I/O7 NC A18 A17 NC I/O3
G I/O8 OE CE A16 A15 I/O4
H A9 A10 A11 A12 A13 A14
w U.coSelection guide
et4Maximum address access time
eMaximum outputenable access time
ShMaximum operating current
ataMaximum CMOS standby current
Industrial
Commercial
–10
10
4
180
170
5
–12
12
5
160
150
5
–15
15
6
140
130
5
–20 Unit
20 ns
7 ns
110 mA
100 mA
5 mA
www.D2/12/04, v. 1.2
Alliance Semiconductor
P. 1 of 10
Copyright © Alliance Semiconductor. All rights reserved.
1 page AS7C34096A
®
Write cycle (over the operating range)11
–10
Parameter
Symbol Min Max
Write cycle time
tWC 10
–
Chip enable (CE) to write end
tCW 7
–
Address setup to write end
tAW 7
–
Address setup time
tAS 0
–
Write pulse width (OE = high) tWP1 7
–
Write pulse width (OE = low
tWP2 10
–
Address hold from end of write tAH
0
–
Write recovery time
tWR 0
–
Data valid to write end
tDW 5
–
Data hold time
tDH 0
–
Write enable to output in high Z tWZ
0
5
Output active from write end
tOW 3
–
–12
Min Max
12 –
8–
8–
0–
8–
12 –
0–
0–
6–
0–
06
3–
–15
Min Max
15 –
10 –
10 –
0–
10 –
15 –
0–
0–
7–
0–
07
3–
–20
Min Max
20 –
12 –
12 –
0–
12 –
20 –
0–
0–
9–
0–
09
3–
Unit Notes
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns 4, 5
ns 4, 5
ns 4, 5
Write waveform 1 (WE controlled)10,11
tWC
Address
WE
DIN
DOUT
tAW
tWP
tAS
tWZ
tWR
tAH
tDW
Data valid
tDH
tOW
2/12/04, v. 1.2
Alliance Semiconductor
P. 5 of 10
5 Page |
Páginas | Total 10 Páginas | |
PDF Descargar | [ Datasheet AS7C34096A.PDF ] |
Número de pieza | Descripción | Fabricantes |
AS7C34096 | (AS7C34096 / AS7C4096) 5V/3.3V 512K X8 CMOS SRAM | Alliance Semiconductor Corporation |
AS7C34096 | 5V/3.3V 512K X 8 CMOS SRAM | Alliance Semiconductor |
AS7C34096A | 3.3V 512K X8 CMOS SRAM | Alliance Semiconductor Corporation |
AS7C34096LL | Low Power CMOS SRAM | Alliance Semiconductor |
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