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PDF LM5070SDX-80 Data sheet ( Hoja de datos )
| Número de pieza | LM5070SDX-80 | |
| Descripción | Integrated Power Over Ethernet PD Interface and PWM Controller | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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December 2004
LM5070
Integrated Power Over Ethernet PD Interface and PWM
Controller
General Description
The LM5070 power interface port and pulse width modula-
tion (PWM) controller provides a complete integrated solu-
tion for Powered Devices (PD) that connect into Power over
Ethernet (PoE) systems. The LM5070 integrates an 80V,
400mA line connection switch and associated control for a
fully IEEE 802.3af compliant interface with a full featured
current mode pulse width modulator dc-dc converter. All
power sequencing requirements between the controller in-
terface and switch mode power supply (SMPS) are inte-
grated into the IC. Two options are available providing either
an 80% maximum duty cycle limit with slope compensation
(on the –80 suffix) device or a 50% maximum duty cycle limit
and no slope compensation on the (–50 suffix) device.
Features
n Fully Compliant 802.3af Power Interface Port
n 80V, 1Ω, 400 mA Internal MOSFET
n Programmable Inrush Current Limit
n Detection Resistor Disconnect Function
n Programmable Classification Current
n Programmable Under-voltage Lockout with
Programmable Hysteresis
n Thermal Shutdown Protection
n Current Mode Pulse Width Modulator
n Supports both Isolated and Non-Isolated Applications
n Error Amplifier and Reference for Non-Isolated
Applications
n Programmable Oscillator Frequency
n Programmable Soft-start
n 80% Maximum Duty Cycle Limiter, Slope Compensation
(-80 device)
n 50% Maximum Duty Cycle Limiter, No Slope
Compensation (-50 device)
n 800 mA Peak Gate Driver
Packages
n TSSOP-16
n LLP-16 (5 mm x 5 mm)
© 2004 National Semiconductor Corporation DS201200
20120001
www.national.com
1 page  
Electrical Characteristics (Note 3) (Continued)
Specifications in standard type face are for TJ= +25˚C and those in boldface type apply over the full operating junction tem-
perature range. Unless otherwise specified: VIN = 48V, VCC = 10V, RT = 30.3kΩ.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VCC Supply
VCC UVLO (Rising)
VccReg –
300mV
VccReg –
100mV
VCC UVLO (Falling)
Supply Current (Icc)
Cload = 0
5.9
6.25
6.6 V
1.5 3 mA
Error Amplifier
GBW
Gain Bandwidth
4 MHz
DC Gain
75 dB
Input Voltage
FB = COMP
1.219
1.281
V
1.212
1.288
COMP Sink Capability
FB=1.5V COMP=1V
5
20
mA
Current Limit
ILIM Delay to Output
CS step from 0 to 0.6V,
20
ns
time to onset of OUT
transition (90%)
Cycle by Cycle Current Limit
0.44
0.5
0.56
V
Threshold Voltage
Leading Edge Blanking Time
55 ns
CS Sink Impedance (clocked)
25 55 Ω
Softstart
Softstart Current Source
7 10 13 uA
Oscillator(Note 5)
Frequency1
175 200 225 KHz
(RT = 30.3K)
Frequency2
505 580 665 KHz
(RT = 10.5K)
Sync threshold
3.1 3.8 V
PWM Comparator
Delay to Output
COMP set to 2V
25 ns
CS stepped 0 to 0.4V,
time to onset of OUT
transition low
Min Duty Cycle
COMP=0V
0%
Max Duty Cycle (-80 Device)
80 %
Max Duty Cycle (-50 Device)
50 %
COMP to PWM Comparator
0.33
Gain
COMP Open Circuit Voltage
4.5 5.4 6.3 V
COMP Short Circuit Current
COMP= 0V
0.6 1.1 1.5 mA
Slope Compensation
Slope Comp Amplitude
Delta increase at PWM
105 mV
(LM5070-80 Device Only)
Comparator to CS
Output Section
Output High Saturation
Output Low Saturation
Rise time
Iout = 50mA,
VCC - VOUT
Iout = 100mA
Cload = 1nF
0.25
0.25
15
0.75
0.75
V
V
ns
Fall time
Cload = 1nF
15 ns
5 www.national.com
5 Page 
TABLE 1. Operating Modes With Respect to Input
Voltage
Input Voltage
VIN wrt VEE
1.8V to 10.0V
12.5V to 20.5V
23.0V to UVLO
Rising Vth
75V to UVLO
Falling Vth
Mode of
Operation
Detection
(Signature)
Classification
Awaiting Full
Power
Normal Powered
Operation
An external signature resistor is connected to VEE when VIN
exceeds 1.8V, initiating detection mode. During detection
mode, quiescent current drawn by the LM5070 is less than
10uA. Between 10.0V and 12.5V, the device enters classifi-
cation mode and the signature resistor is disabled. The
nominal range for classification mode is 11.5V to 21.5V. The
classification current is turned off once the classification
range voltage is exceeded, to reduce power dissipation.
Between 21.5V and UVLO release, the device is in a
standby state, awaiting the input voltage to reach the opera-
tional range to complete the power up sequence. Once the
VIN voltage increases above the upper UVLO threshold volt-
age, the internal power MOSFET is enabled to deliver a
constant current to charge the input capacitor of the dc-dc
converter. When the MOSFET Vds voltage falls below 1.5V,
the internal Power Good signal enables the SMPS controller.
The LM5070 is specified to operate with an input voltage as
high as 75V. The SMPS controller and internal MOSFET are
disabled when VIN falls to the lower UVLO threshold.
Detection Signature
To detect a potential powered device candidate, the PSE will
apply a voltage from 2.8V to 10V across the input terminals
of the PD. The voltage can be of either polarity so a diode
barrel network is required on both lines to ensure this capa-
bility. The PSE will take two measurements, separated by at
least 1V and 2ms of time. The voltage ramp between mea-
surement points will not exceed 0.1V/us. The delta voltage /
delta current calculation is then performed; if the detected
impedance is above 23.75kΩ and below 26.25kΩ, the PSE
will consider a PD to be present. If the impedance is less
than 15kΩ or greater than 33kΩ a PD will be considered not
present and will not receive power. Impedances between
these values may or may not indicate the presence of a valid
PD. The LM5070 will enable the signature resistor at a
controller input voltage of 1.5V to take into account the diode
voltage drops. The PSE will tolerate no more than 1.9V of
offset voltage (caused by the external diodes) or more than
10uA of offset current (bias current). The input capacitance
must be greater than 0.05uF and less than 0.12uF. To in-
crease efficiency, the signature resistor is disabled by the
LM5070 controller once the input voltage is above the de-
tection range (> 11V).
Classification
To classify the PD, the PSE will present a voltage between
14.5V and 20.5V to the PD. The LM5070 enables classifica-
tion mode at a nominal input voltage of 11.5V. An internal
1.5V linear regulator and an external resistor connected to
the RCLASS pin provide classification programming current.
Table 2 shows the external classification resistor required for
a particular class.
The classification current flows through the IC into the clas-
sification resistor. The suggested resistor values take into
account the bias current flowing into the IC. A different
desired RCLASS can be calculated by dividing 1.5V by the
desired classification current.
Per the IEEE 802.3af specification, classification is optional,
and the PSE will default to class 0 if a valid classification
current is not detected. If PD classification is not desired
(i.e., Class 0), simply leave the RCLASS pin open. The
classification time period may not last longer then 75ms as
per IEEE 802.3af. The LM5070 will remain in classification
mode until VIN is greater than 22V.
TABLE 2. Classification Levels and Required External
Resistors
Class PMIN PMAX ICLASS ICLASS RCLASS
(MIN) (MAX)
0 0.44W 12.95W 0mA 4mA Open
1 0.44W 3.84W 9mA 12mA 150Ω
2 3.84W 6.49W 17mA 20mA 82.5Ω
3 6.49W 12.95W 26mA 30mA 53.6Ω
4 Reserved Reserved 36mA 44mA 38.3Ω
Undervoltage Lockout (UVLO)
The IEEE 802.3af specification states that the PSE will
supply power to the PD within 400ms after completion of
detection. The LM5070 contains a programmable line Under
Voltage Lock Out (UVLO) circuit. The first resistor should be
connected between the VIN to UVLO pins; the bottom resis-
tor in the divider should be connected between the UVLO
and UVLORTN pins. The bottom resistor should not be tied
to VEE because any current from VIN to VEE will cause the
system to violate the 10uA maximum offset current specifi-
cation during detection mode.
The divider must be designed such that the voltage at the
UVLO pin equals 2.0V when VIN reaches the desired mini-
mum operating level. If the UVLO threshold is not met, the
interface control and SMPS control will remain in standby.
UVLO hysteresis is accomplished with an internal 10uA
current source that is switched on and off into the impedance
of the UVLO set point divider. When the UVLO threshold is
exceeded, the current source is activated to instantly raise
the voltage at the UVLO pin. When the UVLO pin voltage
falls below the 2.00V threshold, the current source is turned
off, causing the voltage at the UVLO pin to fall. The LM5070
UVLO thresholds cannot be programmed lower than 23V,
otherwise the device would operate in classification mode
with both the classification current source and the SMPS
enabled. The combined power dissipation of these two func-
tions could exceed the maximum power dissipation of the
package.
There are many additional uses for the UVLO pin. The UVLO
function can also be used to implement a remote enable /
disable function. Pulling the UVLO pin down below the
UVLO threshold disables the interface and SMPS controller.
Power Supply Operation / Current
Limit Programming
Once the UVLO threshold has been satisfied, the interface
controller of the LM5070 will charge up the SMPS input
capacitor through the internal power MOSFET. This load
11 www.national.com
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| PDF Descargar | [ Datasheet LM5070SDX-80.PDF ] | |
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