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PDF MC74AC109 Data sheet ( Hoja de datos )
| Número de pieza | MC74AC109 | |
| Descripción | Dual JK Positive Edge Triggered Flip-Flop | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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EMDduCga7el4-JATKSCrhi1Pgee0got9es4,UirteM.icdvoCemF7l4ipA-CFTlo1p09The MC74AC109/74ACT109 consists of two high–speed
tacompletely independent transition clocked JK flip–flops. The clocking
operation is independent of rise and fall times of the clock waveform.
aThe JK design allows operation as a D flip–flop (refer to
.DMC74AC74/74ACT74 data sheet) by connecting the J and K inputs
wtogether.
wAsynchronous Inputs:
w LOW input to SD (Set) sets Q to HIGH level
mLOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
oSimultaneous LOW on CD and SD makes both Q and Q HIGH
.c• Outputs Source/Sink 24 mA
• ′ACT109 Has TTL Compatible Inputs
UVCC CD2
16 15
J2
14
K2 CP2 SD2 Q2
13 12 11 10
Q2
9
t4CD J
K CP SD Q
Q
eCD1
eJ1 K1 CP1 SD1 Q1 Q1
h1 2 3 4 5 6 7 8
CD1 J1 K1 CP1 SD1 Q1 Q1 GND
SFigure 1. Pinout; 16–Lead Packages Conductors
ta(Top View)
aPIN ASSIGNMENT
PIN FUNCTION
.DJ1, J2, K1, K2
CP1, CP2
wCD1, CD2
SD1, SD2
wQ1, Q2, Q1,
w .DataSheet4U.comQ2
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
http://onsemi.com
16
1
16
1
16
1
DIP–16
N SUFFIX
CASE 648
SO–16
D SUFFIX
CASE 751B
TSSOP–16
DT SUFFIX
CASE 948F
16
1
EIAJ–16
M SUFFIX
CASE 966
ORDERING INFORMATION
Device
Package
Shipping
MC74AC109N
PDIP–16 25 Units/Rail
MC74ACT109N
PDIP–16 25 Units/Rail
MC74AC109D
SOIC–16 48 Units/Rail
MC74ACT109D
SOIC–16 48 Units/Rail
MC74AC109DR2 SOIC–16 2500 Tape & Reel
MC74ACT109DR2 SOIC–16 2500 Tape & Reel
MC74AC109DT TSSOP–16 96 Units/Rail
MC74ACT109DT TSSOP–16 96 Units/Rail
MC74AC109DTR2 TSSOP–16 2500 Tape & Reel
MC74ACT109DTR2 TSSOP–16 2500 Tape & Reel
MC74AC109M
MC74ACT109M
EIAJ–16
EIAJ–16
50 Units/Rail
50 Units/Rail
MC74AC109MEL EIAJ–16 2000 Tape & Reel
MC74ACT109MEL EIAJ–16 2000 Tape & Reel
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 111 of this data sheet.
www Semiconductor Components Industries, LLC, 2001
106
Publication Order Number:
May, 2001 – Rev. 5
MC74AC109/D
1 page  
MC74AC109, MC74ACT109
DC CHARACTERISTICS (continued)
Symbol
Parameter
VOL
Maximum Low Level
Output Voltage
VCC
(V)
4.5
5.5
74ACT
74ACT
TA = +25°C
TA =
–40°C to
+85°C
Typ Guaranteed Limits
0.001 0.1
0.001 0.1
0.1
0.1
4.5 –
5.5 –
IIN Maximum Input
Leakage Current
5.5 –
∆ICCT
Additional Max. ICC/Input
5.5 0.6
IOLD
IOHD
†Minimum Dynamic
Output Current
5.5 –
5.5 –
ICC Maximum Quiescent
Supply Current
5.5 –
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
0.36
0.36
±0.1
–
–
–
4.0
0.44
0.44
±1.0
1.5
75
–75
40
Unit Conditions
V IOUT = 50 µA
*VIN = VIL or VIH
V 24 mA
IOL 24 mA
µA VI = VCC, GND
mA VI = VCC – 2.1 V
mA VOLD = 1.65 V Max
mA VOHD = 3.85 V Min
µA VIN = VCC or GND
AC CHARACTERISTICS (For Figures and Waveforms – See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74ACT
74ACT
Symbol
Parameter
VCC*
(V)
TA = +25°C
CL = 50 pF
Min Typ Max
TA = –40°C
to +85°C
CL = 50 pF
Min Max
Unit
Fig.
No.
fmax
Maximum Clock
Frequency
5.0 145 –
– 125 –
MHz 3–3
tPLH
Propagation Delay
CPn to Qn or Qn
tPHL
Propagation Delay
CPn to Qn or Qn
tPLH
Propagation Delay
CDn or SDn to Qn or Qn
tPHL
Propagation Delay
CDn or SDn to Qn or Qn
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
5.0 4.0
5.0 3.0
5.0 2.5
5.0 2.5
– 11.0 3.5 13.0
– 10.0 2.5 11.5
– 9.5 2.0 10.5
– 10.0 2.0 11.5
ns
ns
ns
ns
3–6
3–6
3–6
3–6
AC OPERATING REQUIREMENTS
Symbol
Parameter
ts
Set–up Time, HIGH or LOW
Jn or Kn to CPn
th
Hold Time, HIGH or LOW
Jn or Kn to CPn
tw
Pulse Width
CPn or CDn or SDn
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
74ACT
74ACT
VCC*
(V)
TA = +25°C
CL = 50 pF
TA = –40°C
to +85°C
CL = 50 pF
Unit
Fig.
No.
Typ Guaranteed Minimum
5.0 –
2.0
2.5 ns 3–9
5.0 –
2.0
2.0 ns 3–9
5.0 –
5.0
6.0 ns 3–6
http://onsemi.com
110
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| PDF Descargar | [ Datasheet MC74AC109.PDF ] | |
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